VHDL-FPGA-Verilog List Page 383

VHDL-FPGA-Verilog list

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decoder_7_SEG_1 Downloaded：0: this files in Quartus 2 are decoder
Date : 2025-06-10 Size : 115kb User : woo
keypad_7segdis Downloaded：0: this files in Quartus 2 are KEYPAD
Date : 2025-06-10 Size : 16kb User : woo
ALU_2016 Downloaded：0: this files in Quartus 2 are ALU
Date : 2025-06-10 Size : 6kb User : woo
I2C-Master Downloaded：0: I2C Master for Metis to setup MCP4661
Date : 2025-06-10 Size : 3kb User : yupo
MUX_ise12migration Downloaded：0: mux for fpga vhdl code
Date : 2025-06-10 Size : 46kb User : fifi
qpsk-modulation--achieved-by-Verilog Downloaded：0: qpsk modem s Verilog implementation using Verilog language to write achieve qpsk modulation implementation has passed through simulation.
Date : 2025-06-10 Size : 4kb User : daruili
counter-achieved-by-verilog Downloaded：0: The code in Verilog realize the counting function, the main achievement of 29 counts, has been verified by simulation.
Date : 2025-06-10 Size : 2kb User : daruili
divider-achieved-by-verilog Downloaded：0: The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
Date : 2025-06-10 Size : 2kb User : daruili
shfiting-output-achieved-by-verilog Downloaded：0: The code in Verilog realize the shift output function, the main achievement of the input signal shift output has been verified by simulation.
Date : 2025-06-10 Size : 3kb User : daruili
weimafashengqi-achieved-by-verilog Downloaded：0: The code in Verilog realize the M-sequence pseudo-code generation, pseudo-code characteristic equation for the X13+ X7+ X5+ 1, it has been verified by simulation.
Date : 2025-06-10 Size : 3kb User : daruili
UART_send Downloaded：0: Single-byte serial transmit data. It has been tested. Programming language is Verilog.
Date : 2025-06-10 Size : 1kb User : 毛毛
UART_rec Downloaded：0: Verilog language used to write the serial receiver. Send data through the serial port assistant. It can be seen at the data output terminal of the data transmission. (Need to assign your own FPGA pin)
Date : 2025-06-10 Size : 1kb User : 毛毛

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