VHDL-FPGA-Verilog List Page 248

VHDL-FPGA-Verilog list

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digital_clock Downloaded：0: digital clock Vivado learning materials Digital clock design, new construction, import related documents (source)
Date : 2025-05-25 Size : 2kb User : kkoogqw
TMC module control Downloaded：0: control the rotation of the step motor at different position
Date : 2025-05-25 Size : 22kb User : 光头胡子男
VHDL设计100例 Downloaded：0: VHDL source code of the 100 cases
Date : 2025-05-25 Size : 6.33mb User : lovegiving
AD9777 Downloaded：0: AD9777 chip design based on FPGA platform code
Date : 2025-05-25 Size : 286kb User : leopard021224
I2C_slaver_verison3.0 Downloaded：0: I2C slave module, including testbench, the platform is vivado, simulation test passed.
Date : 2025-05-25 Size : 2mb User : wenxulyu
pll_self_rst Downloaded：0: Used to detect false lock problems in ALTERA FPGA PLL applications
Date : 2025-05-25 Size : 471kb User : njithjw
is61lv25616 (1) Downloaded：0: it is fpga is 61lv25616 simple verilog program,complete sram read and write.it can read and write .
Date : 2025-05-25 Size : 1kb User : utopia_xu
sramf Downloaded：0: array to simulate SRAM wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
Date : 2025-05-25 Size : 1kb User : utopia_xu
fpgaasm Downloaded：0: `ifdef tAC_10 //if "`define tAC_10 " at beginning,sentences below are compiled
Date : 2025-05-25 Size : 1kb User : utopia_xu
pgaasm Downloaded：0: 1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read
Date : 2025-05-25 Size : 1kb User : utopia_xu
fpgaasm Downloaded：0: am_IS61LV25616A61LV25616Aam61LV25616AV25616Aam61LV2561
Date : 2025-05-25 Size : 1kb User : utopia_xu
disp Downloaded：0: You can clock and display time.
Date : 2025-05-25 Size : 1kb User : 天快亮了

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