VHDL-FPGA-Verilog List Page 246

VHDL-FPGA-Verilog list

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DE2_Basic_Computer Downloaded：0: Convert DE2 FPGA to Small Computer
Date : 2025-05-25 Size : 1.2mb User : frozeus
mmp Downloaded：0: Electronic puzzle lock
Date : 2025-05-25 Size : 692kb User : ZZZqqq
asyn_fifo Downloaded：0: The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.
Date : 2025-05-25 Size : 1kb User : 叶古
syn_fifo Downloaded：0: The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.
Date : 2025-05-25 Size : 1kb User : 叶古
Estacionamento Downloaded：0: code of a system park, check out
Date : 2025-05-25 Size : 29kb User : nome
test Downloaded：0: Sine wave can be generated through the ROM, the document has complete code, you can download directly
Date : 2025-05-25 Size : 3.42mb User : 哈虎
Nios2_LB0 Downloaded：0: Use the Nios platform to run the LED cycle with the C language
Date : 2025-05-25 Size : 21.27mb User : 大头q
code Downloaded：0: Realize CNN network using HLS tool
Date : 2025-05-25 Size : 9kb User : 蔡宇杰
BCH_VLSI Downloaded：0: BCH Encoder realized using HLS tool. Combinational logic.
Date : 2025-05-25 Size : 13.83mb User : 蔡宇杰
tdc-core-master Downloaded：0: The HDL implementation of TDC function, verified in spartan 6 platform.
Date : 2025-05-25 Size : 984kb User : dragonxu
decoder3_8 Downloaded：0: an decoder 3 to 8 with switch
Date : 2025-05-25 Size : 4.08mb User : jingcuz
uart2bus_latest.tar Downloaded：0: uart sdadasdsadasdasdasda
Date : 2025-05-25 Size : 244kb User : jiannanc

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