VHDL-FPGA-Verilog List Page 252

VHDL-FPGA-Verilog list

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CMI Downloaded：0: CMI is designed for m5 random list, which is should in the project, and it can decode it and get the original m5 list
Date : 2025-05-26 Size : 154kb User : 邵成武
jesd204 Downloaded：0: Xilinx platform jesd204 core example of the use demo
Date : 2025-05-26 Size : 4kb User : kenny2017
Songer Downloaded：0: Butterfly Lovers music performance
Date : 2025-05-26 Size : 491kb User : 执书仗剑
piano Downloaded：0: Electronic piano original work VHDL, using counter frequency division, contains a few simple nursery rhyme, Edik EDA experimental box, there are digital tube and LED display, using keyboard output, two lines, alto treble
Date : 2025-05-26 Size : 1.05mb User : qengleikangjen
crc16 Downloaded：0: a VHDL code for CRC16.
Date : 2025-05-26 Size : 7kb User : camelcc
SDI资料 Downloaded：1: Xilinx official information, , a good introductory information for learning SDI
Date : 2025-05-26 Size : 5.46mb User : 旭旭
LatticeECP3_SERDES_PCS_使用指南 Downloaded：0: LatticeECP3 SERDES/PCS usage guide
Date : 2025-05-26 Size : 1.68mb User : 旭旭
vivado Downloaded：0: vivado 2016.1 & license
Date : 2025-05-26 Size : 5kb User : 旭旭
test1 Downloaded：0: seven-segment decoder
Date : 2025-05-26 Size : 44kb User : LdF!!!
fpga代码 Downloaded：0: The m sequence is generated and the synchronous signal extraction function is realized
Date : 2025-05-26 Size : 116kb User : 两下子
AD9512_test Downloaded：0: Clock chip AD9512 debugging, achieve use successfully
Date : 2025-05-26 Size : 464kb User : 木子朱
PWM Downloaded：0: VHDL code for PWM Generator with Variable Duty Cycle
Date : 2025-05-26 Size : 1kb User : param

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