VHDL-FPGA-Verilog List Page 254

VHDL-FPGA-Verilog list

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键盘实验文件_modify Downloaded：0: Read the keyboard data, and display on the digital tube, frequency speed can reach 100M
Date : 2025-05-26 Size : 12kb User : B_button
zhong5 Downloaded：0: Basys2 development board programmer, can dynamically display the date when the minutes and seconds and temperature on the LCD1602 screen, and you can manually set the alarm clock and the upper temperature limit alarm.
Date : 2025-05-26 Size : 1.99mb User : 陈诚
JTAG_Example0_Verilog Downloaded：0: tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org)
Date : 2025-05-26 Size : 377kb User : ZhouGuofei
ARM JTAG Debug Downloaded：0: OPEN-JTAG Development Group.
Date : 2025-05-26 Size : 452kb User : ZhouGuofei
Lab3 Downloaded：0: Use this code to practice zynq library
Date : 2025-05-26 Size : 6kb User : suni
spi-master Downloaded：1: code for Master side
Date : 2025-05-26 Size : 119kb User : suni
SPI-Master-master Downloaded：0: Use code for Maser SPI
Date : 2025-05-26 Size : 12kb User : suni
2015_2_zynq_labdocs_pdf Downloaded：0: These are bocks for Zynq FPGA
Date : 2025-05-26 Size : 4.3mb User : suni
eda Downloaded：0: Based on VHDL+ FPGA design of the DDS signal has been through mode
Date : 2025-05-26 Size : 196kb User : 丢丢的人生
UART Downloaded：0: UART Verilog source hope useful for all!
Date : 2025-05-26 Size : 1kb User : qcleo
Freq_gen Downloaded：0: XILINX frequency divider 100MHz, 1KHz, 1Hz
Date : 2025-05-26 Size : 991kb User : hush_puppy
vga_pingpong Downloaded：0: Development of VGA display based on FPGA
Date : 2025-05-26 Size : 997kb User : 湾仔

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