VHDL-FPGA-Verilog List Page 257

VHDL-FPGA-Verilog list

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LCD12864 Downloaded：0: Lcd12864 Chinese display. You can change the code by querying ASCII.
Date : 2025-05-26 Size : 1kb User : 刘宇洋
VGA Downloaded：0: Vga with verilog display colorbar image. Includes VGA driver with a resolution of 640* 480.
Date : 2025-05-26 Size : 1kb User : 刘宇洋
Butterfly_lovers_beef Downloaded：0: Verilog prepared buzzer music Butterfly Lovers . The system clock is 50MHz.
Date : 2025-05-26 Size : 1kb User : 刘宇洋
async_fifo Downloaded：0: Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)
Date : 2025-05-26 Size : 1kb User : 刘宇洋
pwm_generate_module Downloaded：0: Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
Date : 2025-05-26 Size : 1kb User : 刘宇洋
cla_16bit Downloaded：0: verilog 16bit carry lookahead adder
Date : 2025-05-26 Size : 1kb User : uiop7890
qiangda Downloaded：0: Responder, 3 answer, that corresponds to three switches, who first press, LED output display
Date : 2025-05-26 Size : 1.76mb User : 樊雪婵
ALU_4_operations Downloaded：0: unid logic aritmetic- four options
Date : 2017-06-02 Size : 80.05kb User : fitnowredribbon
9363 Downloaded：0: ad9363 interface.tdd mode.
Date : 2025-05-26 Size : 6kb User : sgeb
USB_GPIF-II Downloaded：0: fpga generate two lane video, and transmit them through GPIF II interface. test cy2014
Date : 2025-05-26 Size : 10kb User : haoluo
LED Downloaded：0: led test， shift
Date : 2025-05-26 Size : 1kb User : haoluo
SIN_COS Downloaded：0: fpga generate sin waveform,test passed
Date : 2025-05-26 Size : 7kb User : haoluo

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