VHDL-FPGA-Verilog List Page 2259

VHDL-FPGA-Verilog list

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ztj Downloaded：0: Moore state machine testing procedures, the sequence detector, 1100101 test
Date : 2025-11-24 Size : 257kb User : xuefj
balu Downloaded：0: Responder lab reports, curriculum design, graduate design, MAX+ PLUS
Date : 2025-11-24 Size : 245kb User : xuefj
boxing Downloaded：0: Waveform generator, a selection module can be square wave sine pulse
Date : 2025-11-24 Size : 10kb User : xuefj
a-new-mthod-of-cic3_decimator Downloaded：0: a new method of CIC
Date : 2025-11-24 Size : 1kb User : 罗辉
oc_i2c_master Downloaded：0: the IIC bus control VHDL source code and ，Quartus2 can create the corresponding IP in nuclear
Date : 2025-11-24 Size : 203kb User : 陶文辉
inputoutput Downloaded：0: this code is simulation for input and output into VHDL, you can run at ModelSim and see the signal Wave
Date : 2025-11-24 Size : 1kb User : rino
Digital-Responder Downloaded：0: ① The EDA training instrument I/O devices and PLD chip intelligent electronic Responder count. ② intelligent electronic Responder Responder can accommodate four participants, each with an answer in button. ③ circuit with
Date : 2025-11-24 Size : 2.09mb User : wtm_dxyb
Calendar Downloaded：0: ① The EDA training instrument I/O devices and PLD chip digital calendar design. ② Figures calendar can display year, month, day, hours, minutes and seconds. ③ instrument training with EDA eight out of eight two-screen di
Date : 2025-11-24 Size : 4.76mb User : wtm_dxyb
Ep2c5q208 Downloaded：0: On the FPGA (EP2c5q208) schematic
Date : 2025-11-24 Size : 6kb User : 陈定锋
urisc_2011 Downloaded：0: This is a urisc job, build a single instruction for the processor,
Date : 2025-11-24 Size : 3kb User : 张铖
state_FPGA Downloaded：0: FPGA-based state machine, used in high-speed A / D sampling, the test
Date : 2025-11-24 Size : 263kb User : 宋珂
timer Downloaded：0: Timer Module
Date : 2025-11-24 Size : 2kb User : 刘源

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