VHDL-FPGA-Verilog List Page 2256

VHDL-FPGA-Verilog list

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dds Downloaded：0: The signal generator based on VHDL DDS, can produce square wave, triangle wave, sine wave, amplitude, frequency, phase can be adjusted
Date : 2025-11-24 Size : 1.55mb User :
sin Downloaded：0: The sine signal generator based on VHDL, experience card
Date : 2025-11-24 Size : 137kb User :
Counter24hour Downloaded：0: A 24 binary counter programmed with VHDL language.A pulse input, a reset input, four output BCD code. It is one of my total 9 modules that are used to design a digital clock.
Date : 2025-11-24 Size : 166kb User : chzhsen
Counter60min Downloaded：0: A 60 binary counter(for minute) programmed with VHDL language.A pulse input, a reset input, eight BCD code output BCD code, a carry bit output. It is one of my total 9 modules that are used to design a digital clock.
Date : 2025-11-24 Size : 203kb User : chzhsen
Counter60sec Downloaded：0: A 60 binary counter（for second） programmed with VHDL language.A pulse input, a reset input, eight BCD code output. It is one of my total 9 modules that are used to design a digital clock.
Date : 2025-11-24 Size : 144kb User : chzhsen
Debounce Downloaded：0: Programmed with VHDL.A debouncing circuit which is part of a digital clock designed on a CPLD development board.The module is independent from others and is useful for learning deboucing methods.It is one of my total 9 m
Date : 2025-11-24 Size : 195kb User : chzhsen
Displayer Downloaded：0: Programmed with VHDL.The decoding and displaying circuit for 8-segments displayer.It outputs the data of hour,minute and second in order with dynamic scaning method.It is one of my total 9 modules that are used to design
Date : 2025-11-24 Size : 147kb User : chzhsen
Distributer Downloaded：0: Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used to design a digital clock.
Date : 2025-11-24 Size : 258kb User : chzhsen
FlashTime Downloaded：0: Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let the user know time revised. This module implemen
Date : 2025-11-24 Size : 140kb User : chzhsen
RvsTime Downloaded：0: Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour or minute. It recepts an impulse input from a key and the currently revised time will increase by 1 for
Date : 2025-11-24 Size : 116kb User : chzhsen
ADigCLK Downloaded：0: A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all submodules into a complete digital clock.It is one of my total 9 modules that a
Date : 2025-11-24 Size : 505kb User : chzhsen
S1_12864lcd Downloaded：0: control 128x64 lcd display by fpga
Date : 2025-11-24 Size : 365kb User : 东

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