VHDL-FPGA-Verilog List Page 2261

VHDL-FPGA-Verilog list

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AD Downloaded：0: The AD converter based EP1C6Q240 code, novice to understand
Date : 2025-11-24 Size : 333kb User :
counter Downloaded：0: Counter EP1C6Q240 based settings, easy to understand, debug through
Date : 2025-11-24 Size : 1.78mb User :
DA Downloaded：0: The DA conversion based EP1C6Q240 code, easy to understand, debug through, based on quartus 6.0
Date : 2025-11-24 Size : 206kb User :
FREQ Downloaded：0: Based on the frequency meter EP1C6Q240 design, easy to understand, debug through, based on quartus6.0
Date : 2025-11-24 Size : 218kb User :
LED Downloaded：0: The water-based EP1C6Q240 light design, easy to understand, debug through, based on quartus6.0
Date : 2025-11-24 Size : 244kb User :
LOCK Downloaded：0: Based on EP1C6Q240 password lock design, easy to understand, debug through, based on quartus6.0
Date : 2025-11-24 Size : 407kb User :
MOTOR Downloaded：0: EP1C6Q240 stepper motor based design, easy to understand, debug through, based on quartus6.0
Date : 2025-11-24 Size : 280kb User :
rs232c Downloaded：0: Serial rs232 communication based EP1C6Q240 code design, easy to understand, debug through, based on quartus6.0
Date : 2025-11-24 Size : 360kb User :
ep2c35_4_9_motor Downloaded：0: it is writen by VHDL,the program generate PWMs to control the motor
Date : 2025-11-24 Size : 81kb User : Nevin Young
ep2c35_3.14_beep Downloaded：0: this program is writen by verilog . it is used to trigger the beep which is in the FPGA s develop board
Date : 2025-11-24 Size : 48kb User : Nevin Young
ep2c35_4_15_signal_generator Downloaded：0: This program is writen by verilog HDL.it is for generate waves in FPGA
Date : 2025-11-24 Size : 138kb User : Nevin Young
ep2c35_3.8_full_add Downloaded：0: this program is writen by verilog HDL.it is the full adder for FPGA.users can read the result from the LEDs.
Date : 2025-11-24 Size : 49kb User : Nevin Young

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