VHDL-FPGA-Verilog List Page 2262

VHDL-FPGA-Verilog list

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ep2c35_5_5_fir_test Downloaded：0: Filter design using fpga to calculate the speed, reliability! Filter works well, trustworthy
Date : 2025-11-24 Size : 386kb User : 伍龙
ep2c35_5_6_fft_test Downloaded：0: Fpga to implement the use of fast Fourier transform, fast, stable and accurate calculations.
Date : 2025-11-24 Size : 786kb User : 伍龙
VHDL Downloaded：0: The frequency of an points based on VHDL program
Date : 2025-11-24 Size : 5kb User : 白银河
Digital_VLSI_Design Downloaded：0: Digital VLSI Design with Verilog_A Textbook from Silicon Valley Technical Institute 1402084455.rar
Date : 2025-11-24 Size : 9.82mb User : 黃文
Digital_Design_with_CPLD Downloaded：0: Digital Design with CPLD
Date : 2025-11-24 Size : 7.07mb User : 黃文
FPGA-wireless] Downloaded：0: FPGA wirele
Date : 2025-11-24 Size : 300kb User : liuchao
Frame-synchronization Downloaded：0: Frame synchronization FPGA
Date : 2025-11-24 Size : 251kb User : liuchao
viterbi219 Downloaded：0: -(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform
Date : 2025-11-24 Size : 10kb User : matt
multiprocessor Downloaded：0: NIOS-core routine over 4 cpu NIOS debug multi-core debug 4 cpu routines
Date : 2025-11-24 Size : 2.48mb User : hanmy
DDS Downloaded：0: DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
Date : 2025-11-24 Size : 927kb User : 郭强
PhaseMeasure Downloaded：0: The measured frequency of Altera FPGA-based project file, based on the frequency measurement logic gates
Date : 2025-11-24 Size : 329kb User : 郭强
convcode Downloaded：0: Modelsim-based convolution code (2,1,7) and Verilog implementation of direct generation
Date : 2025-11-24 Size : 17kb User : 郭强

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