VHDL-FPGA-Verilog List Page 2255

VHDL-FPGA-Verilog list

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ddr_sdr Downloaded：0: ddr ram controller,designed by vhdl
Date : 2025-11-24 Size : 113kb User : 东
decoder Downloaded：0: this project is the mp3 decoder， designed by vhdl
Date : 2025-11-24 Size : 34kb User : 东
memory_cores Downloaded：0: general ram source package，include dual port ram，single port ram，fifo，etc.
Date : 2025-11-24 Size : 36kb User : 东
ram_wb Downloaded：0: wide word ram，desinged by vhdl on quartus platform
Date : 2025-11-24 Size : 836kb User : 东
a_vhd_16550_uart Downloaded：0: Compatible with 16550 uart, use fpga implementation, multi-platform support
Date : 2025-11-24 Size : 143kb User : 东
VHDLshixianCPU2 Downloaded：0: cpu using verilog vhdl achieve 8-bit CPU to write source code, assembly language can be achieved through the addition and subtraction and other operations by the left right. And the process can be simulated by the ASC in
Date : 2025-11-24 Size : 52kb User : 张梦
jiajian Downloaded：0: In QuARRTER 2 environment to run, to achieve selective addition and subtraction techniques, hardware description language.
Date : 2025-11-24 Size : 1kb User : ethan
Ammeter3 Downloaded：0: 8-bit high-precision digital display with a relay-controlled prepayment meter schematic
Date : 2025-11-24 Size : 71kb User : 张仁良
FPS200design Downloaded：0: FPS200' s. . Sch map, hardware design methods
Date : 2025-11-24 Size : 46kb User : 范晓
vga_nios2 Downloaded：0: nios2 vga controller (unsing flash memory)
Date : 2025-11-24 Size : 15.37mb User : kimyeonwoo
four Downloaded：0: University of VHDL test subjects reported four full adder design report
Date : 2025-11-24 Size : 203kb User : 胡飞
shift194 Downloaded：0: 194 of the Verilog design, a relatively simple design ideas
Date : 2025-11-24 Size : 104kb User : 刘进向

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