194 of the Verilog design, a relatively simple design ideas

shift194\shift194.asm.rpt
........\shift194.done
........\shift194.eda.rpt
........\shift194.fit.rpt
........\shift194.fit.summary
........\shift194.flow.rpt
........\shift194.map.rpt
........\shift194.map.summary
........\shift194.pin
........\shift194.pof
........\shift194.qpf
........\shift194.qsf
........\shift194.qws
........\shift194.sim.rpt
........\shift194.tan.rpt
........\shift194.tan.summary
........\shift194.v
........\Waveform1.vwf
........\shift194_assignment_defaults.qdf
........\shift194.map.smsg
........\shift194.vwf
........\db\shift194.db_info
........\..\shift194.sim.qmsg
........\..\shift194.sim.hdb
........\..\shift194.fnsim.qmsg
........\..\shift194.cbx.xml
........\..\shift194.hif
........\..\shift194.hier_info
........\..\shift194.psp
........\..\shift194.dbp
........\..\shift194.syn_hier_info
........\..\shift194.fnsim.hdb
........\..\shift194.eds_overflow
........\..\shift194.sim.vwf
........\..\shift194.sim.rdb
........\..\wed.zsf
........\..\shift194.map.qmsg
........\..\shift194.rtlv_sg.cdb
........\..\shift194.rtlv.hdb
........\..\shift194.rtlv_sg_swap.cdb
........\..\shift194.pre_map.hdb
........\..\shift194.pre_map.cdb
........\..\shift194.map.logdb
........\..\shift194.sgdiff.cdb
........\..\shift194.sgdiff.hdb
........\..\shift194.sld_design_entry_dsc.sci
........\..\shift194.map.cdb
........\..\shift194.map.hdb
........\..\shift194.fit.qmsg
........\..\shift194.cmp.logdb
........\..\shift194.asm.qmsg
........\..\shift194.tan.qmsg
........\..\shift194.cmp.tdb
........\..\shift194.cmp0.ddb
........\..\shift194.cmp.cdb
........\..\shift194.eda.qmsg
........\..\shift194.cmp.hdb
........\..\shift194.cmp.rdb
........\..\shift194.rpp.qmsg
........\..\shift194.sgate.rvd
........\..\shift194.sgate_sm.rvd
........\..\shift194.sld_design_entry.sci
........\..\shift194.eco.cdb
........\symbols\viewdraw\shift194.xml
........\.......\viewdraw
........\db
........\symbols
shift194

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