VHDL-FPGA-Verilog List Page 1322

VHDL-FPGA-Verilog list

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VHDL-stopwatch-reports-and-code Downloaded：0: Using VHDL the digital stopwatch design practice, and functional verification of FPGA download!
Date : 2025-08-27 Size : 1.81mb User : 一个好人
VHDL-counter-code Downloaded：0: With WHDL counter module design and functional verification using FPGA!
Date : 2025-08-27 Size : 560kb User : 一个好人
VHDL-music-generator-report-code Downloaded：0: VHDL music generator and FPGA verification! The report contains a detailed code of each module, and the simulation waveform!
Date : 2025-08-27 Size : 75kb User : 一个好人
FPGACPLD-design-tools-Xilinx-ISE Downloaded：0: FPGA/CPLD design tools ─ ─ Xilinx ISE explain the use of! x details use XilinxISE!
Date : 2025-08-27 Size : 11.79mb User : 一个好人
UART-based-on-FPGA Downloaded：0: FPGA implementation of the UART, engineering and design documentation for instructions
Date : 2025-08-27 Size : 1.95mb User : 丁俊辉
S7_PS2_LCD Downloaded：0: 1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display input characters, of which the keyboard on backspce key is used to clear the screen, when the lcd display full of character, press
Date : 2025-08-27 Size : 591kb User : 丁俊辉
S6_VGA Downloaded：0: 1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic a
Date : 2025-08-27 Size : 3.05mb User : 丁俊辉
S3_WAVE Downloaded：0: 1, the experimental simulation of the sine function generator, logic analyzer view waveform 3/proj/simulation directory in modelsim simulation
Date : 2025-08-27 Size : 24.36mb User : 丁俊辉
the_design_basedonfpga Downloaded：0: The 1. Clkdiv modeling clock divider 2. Counter introduced count modeling the The 3. Dtrig 4. Jktrig introduce the modeling of the JK flip-flop 5 introduces the D flip-flop modeling. Shiftreg introduces the modeling of s
Date : 2025-08-27 Size : 563kb User : 丁俊辉
duanx Downloaded：0: Achieve ultra-simple, ultra-clear any integer divider function fully prepared in. Code is clearly understood, and naturally less occupied. Perfectly suited to the call.
Date : 2025-08-27 Size : 1kb User : 段雄
VHDLcommen-erro-in-all Downloaded：0: VHDL Programming Common Errors collection. Most of these errors is a common mistake for beginners.
Date : 2025-08-27 Size : 677kb User : 段雄
Automatic-beverage-vending-machine Downloaded：0: Drinks vending machine can only be put into hair and a dollar per bottle of $ 2.5 requires the application of state machine design of the system, and to prepare Testbench. Input signal definition: clk: clock input ngrese
Date : 2025-08-27 Size : 1kb User : seven

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