VHDL-FPGA-Verilog List Page 1317

VHDL-FPGA-Verilog list

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a-to-A Downloaded：0: from strings to ASIC
Date : 2025-08-27 Size : 1kb User : 邓海涛
tsxt4 Downloaded：0: Frequency meter, the use of Fpga language design and implementation of frequency measurement, can modify their own, platform type ED2 development board "
Date : 2025-08-27 Size : 643kb User : lufei
niosII_cycloneIII_3c120_fast Downloaded：0: Frequency meter, the use of Fpga language design and implementation of frequency measurement, can modify their own, platform type ED2 development board "
Date : 2025-08-27 Size : 198kb User : lufei
www_onlylz_com@b-do84mw Downloaded：0: nois2 development instance. The application platform is DE2 development board. Implement a simple electronic clock display calendar. The design is simple, convenient
Date : 2025-08-27 Size : 1kb User : lufei
VGA Downloaded：0: Prepared using Verilog HDL VGA display program, image display DE2-70 test by great reference value.
Date : 2025-08-27 Size : 6.48mb User : 李桐
uart Downloaded：0: Prepared by the serial input and output using Verilog HDL program can achieve data transmission test by DE2-70, there is a great reference value.
Date : 2025-08-27 Size : 21.04mb User : 李桐
sdram_mdl Downloaded：0: SDRAM control program written using Verilog HDL DE2-70 test passes, great reference value.
Date : 2025-08-27 Size : 2.54mb User : 李桐
PR-user-guide12.3 Downloaded：0: Reconfigurable fpga user guide, detailing the development process.
Date : 2025-08-27 Size : 2.17mb User : caixuanxian
project1source Downloaded：0: SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state
Date : 2025-08-27 Size : 58kb User : 冷静思
FPGA_LCD_BEST Downloaded：0: This code is directly through debugging in hardware to run
Date : 2025-08-27 Size : 709kb User : 付勇
vhdl_text3 Downloaded：0: Design a data width 8bit depth of 16 the synchronization FIFO (read and write with the same clock), EMPTY, FULL output flag. Requirements FIFO read and write clock frequency of 20MHz, to 1-16 consecutive write FIFO, and
Date : 2025-08-27 Size : 6kb User : jiange
led_display Downloaded：0: Using the fpga chip realize 7 period of digital tube static display 7128
Date : 2025-08-27 Size : 1kb User : xuyawang

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