Design a data width 8bit depth of 16 the synchronization FIFO (read and write with the same clock), EMPTY, FULL output flag. Requirements FIFO read and write clock frequency of 20MHz, to 1-16 consecutive write FIFO, and then filled it read out (read empty so far). Timing simulation above logic

vhdl_text3\t1.bdf
..........\t2.bdf
..........\t3.bdf
vhdl_text3

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