Prepared using Verilog HDL VGA display program, image display DE2-70 test by great reference value.

VGA\db\altsyncram_1mh1.tdf
...\..\altsyncram_4ba1.tdf
...\..\altsyncram_7cc1.tdf
...\..\altsyncram_7ih1.tdf
...\..\altsyncram_c4c1.tdf
...\..\altsyncram_chc1.tdf
...\..\altsyncram_hgd1.tdf
...\..\altsyncram_hhh1.tdf
...\..\altsyncram_kmh1.tdf
...\..\altsyncram_m7c1.tdf
...\..\altsyncram_rfc1.tdf
...\..\decode_9oa.tdf
...\..\decode_opa.tdf
...\..\decode_ppa.tdf
...\..\logic_util_heursitic.dat
...\..\mux_2kb.tdf
...\..\mux_7kb.tdf
...\..\mux_mlb.tdf
...\..\mux_nlb.tdf
...\..\mux_pib.tdf
...\..\prev_cmp_VGA_Ctr.qmsg
...\..\VGA_Ctr.db_info
...\..\VGA_Ctr.eco.cdb
...\..\VGA_Ctr.sld_design_entry.sci
...\greybox_tmp\cbx_args.txt
...\incremental_db\compiled_partitions\VGA_Ctr.db_info
...\..............\...................\VGA_Ctr.root_partition.cmp.cdb
...\..............\...................\VGA_Ctr.root_partition.cmp.dfp
...\..............\...................\VGA_Ctr.root_partition.cmp.hdb
...\..............\...................\VGA_Ctr.root_partition.cmp.kpt
...\..............\...................\VGA_Ctr.root_partition.cmp.logdb
...\..............\...................\VGA_Ctr.root_partition.cmp.rcfdb
...\..............\...................\VGA_Ctr.root_partition.map.cdb
...\..............\...................\VGA_Ctr.root_partition.map.dpi
...\..............\...................\VGA_Ctr.root_partition.map.hbdb.cdb
...\..............\...................\VGA_Ctr.root_partition.map.hbdb.hb_info
...\..............\...................\VGA_Ctr.root_partition.map.hbdb.hdb
...\..............\...................\VGA_Ctr.root_partition.map.hbdb.sig
...\..............\...................\VGA_Ctr.root_partition.map.hdb
...\..............\...................\VGA_Ctr.root_partition.map.kpt
...\..............\README
...\Mif6.mif
...\Mif8bits.mif
...\Mif8bits.ver
...\my_ram.bsf
...\my_ram.qip
...\my_ram.v
...\simulation\modelsim\123.hex
...\..........\........\Hex2.hex
...\..........\........\Hex2.ver
...\..........\........\Mif2.mif
...\..........\........\Mif3_32w.mif
...\..........\........\Mif3_32w.ver
...\..........\........\Mif6.mif
...\..........\........\Mif8bits.mif
...\..........\........\modelsim.ini
...\..........\........\msim_transcript
...\..........\........\rtl_work\@v@g@a_@ctr\verilog.prw
...\..........\........\........\...........\verilog.psm
...\..........\........\........\...........\_primary.dat
...\..........\........\........\...........\_primary.dbs
...\..........\........\........\...........\_primary.vhd
...\..........\........\........\..........._vlg_tst\verilog.prw
...\..........\........\........\...................\verilog.psm
...\..........\........\........\...................\_primary.dat
...\..........\........\........\...................\_primary.dbs
...\..........\........\........\...................\_primary.vhd
...\..........\........\........\.......clk\verilog.prw
...\..........\........\........\..........\verilog.psm
...\..........\........\........\..........\_primary.dat
...\..........\........\........\..........\_primary.dbs
...\..........\........\........\..........\_primary.vhd
...\..........\........\........\my_ram\verilog.prw
...\..........\........\........\......\verilog.psm
...\..........\........\........\......\_primary.dat
...\..........\........\........\......\_primary.dbs
...\..........\........\........\......\_primary.vhd
...\..........\........\........\_info
...\..........\........\........\_vmake
...\..........\........\VGA_clk.vt
...\..........\........\VGA_clk.vt.bak
...\..........\........\VGA_Ctr.hex
...\..........\........\VGA_Ctr.sft
...\..........\........\VGA_Ctr.ver
...\..........\........\VGA_Ctr.vo
...\..........\........\VGA_Ctr.vt
...\..........\........\VGA_Ctr.vt.bak
...\..........\........\VGA_Ctr_fast.vo
...\..........\........\VGA_Ctr_modelsim.xrf
...\..........\........\VGA_Ctr_run_msim_rtl_verilog.do
...\..........\........\VGA_Ctr_run_msim_rtl_verilog.do.bak
...\..........\........\VGA_Ctr_run_msim_rtl_verilog.do.bak1
...\..........\........\VGA_Ctr_run_msim_rtl_verilog.do.bak10
...\..........\........\VGA_Ctr_run_msim_rtl_verilog.do.bak11
...\.........

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