VHDL-FPGA-Verilog List Page 1318

VHDL-FPGA-Verilog list

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lfsr Downloaded：0: the LFSR is coded in VHDL, using a structural description, which is instantiated as a separate component in the top-level design. Then we can get a random number by a pseudorandom number generator based on a linear feedb
Date : 2025-08-27 Size : 2kb User : 宋臣
Sum_of_2_rand Downloaded：0: We produce two 5-bit random numbers and then adds them. The two random numbers are generated by pressing two different push-buttons on the lab board. The addition is controlled by a third button, button3. it can be imple
Date : 2025-08-27 Size : 2kb User : 宋臣
Mulitiplier_Hardwired_Control Downloaded：0: The code is a multiplier that use the structure of datapath and hardwired control. It can be implemented on the Atlys board.
Date : 2025-08-27 Size : 5kb User : 宋臣
int_div Downloaded：0: frequency divider vhdl
Date : 2025-08-27 Size : 1kb User : gongwenbiao
xilinx-fpga-led Downloaded：0: A complete xilinx fpga instance, the completion of the lamp function
Date : 2025-08-27 Size : 489kb User : 胡耀航
Matlab-IIR Downloaded：0: The important aspect of the digital filter is a digital signal processing, digital IIR and FIR filter may be divided into two categories. This article describes the basic design principle of IIR and FIR, as well as how t
Date : 2025-08-27 Size : 790kb User : 王策
oxy Downloaded：0: The memory polynomial method implementations nonlinear filter
Date : 2025-08-27 Size : 1.1mb User : marine
clk Downloaded：0: Verilog code, modelsim simulation and download configuration based on EP2C5Q208C binary frequency
Date : 2025-08-27 Size : 327kb User : zuozuo
round Downloaded：0: The the experimental box standard AD_DA panel D/A converters, a round analog waveform, learning LPM_ROM (1024* 10) the megafunctions the customization and use last Quartus II to complete the design, simulation.
Date : 2025-08-27 Size : 80kb User : 跳跳鱼
data_to_asc Downloaded：0: translate binary to ASIC
Date : 2025-08-27 Size : 1kb User : 邓海涛
asc_to_raw Downloaded：0: from text to binary file
Date : 2025-08-27 Size : 1kb User : 邓海涛
stream_to_asc Downloaded：0: from bianry streams to ASIC
Date : 2025-08-27 Size : 1kb User : 邓海涛

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