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VHDL-FPGA-Verilog list
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Downloaded:0
thank you
Date
: 2025-08-28
Size
: 32kb
User
:
张洪敬
or
Downloaded:0
thank you
Date
: 2025-08-28
Size
: 240kb
User
:
张洪敬
www
Downloaded:0
the design is aimed at three bit digital to multiply
Date
: 2025-08-28
Size
: 3kb
User
:
wanglan
PL2
Downloaded:0
CPLD implementation of digital frequency meter, fully functional
Date
: 2025-08-28
Size
: 1.06mb
User
:
xiaohuan
tri-state-bidirectional-bus
Downloaded:0
Implementation of FPGA in the tri-state bidirectional bus
Date
: 2025-08-28
Size
: 64kb
User
:
神小白
lcd_display
Downloaded:0
two part lcd display
Date
: 2025-08-28
Size
: 889kb
User
:
呵呵
modelsim-sdram-sim
Downloaded:0
Includes sdram testbench, sdram controller, sdram behavior model.
Date
: 2025-08-28
Size
: 182kb
User
:
qiubin
dds_signaltab
Downloaded:0
Direct frequency synthesizer design FPGA-based use QUARTUS vhdl prepared
Date
: 2025-08-28
Size
: 274kb
User
:
bobo
5-15
Downloaded:0
DDS implementations, in XILINX FPGA verification by. Using ROM.
Date
: 2025-08-28
Size
: 8kb
User
:
wh
divider
Downloaded:0
verilog implementation of division operation can be modified. Achieve more wide data.
Date
: 2025-08-28
Size
: 1kb
User
:
wh
FIR_lowpass
Downloaded:0
8 Gaussian low-pass FIR implementation, can be achieved, according to the principle of the higher order FIR.
Date
: 2025-08-28
Size
: 1kb
User
:
wh
8-14
Downloaded:0
The OFDM module implementation, use FFTIP nuclear, can refer to.
Date
: 2025-08-28
Size
: 2kb
User
:
wh
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