Direct frequency synthesizer design FPGA-based use QUARTUS vhdl prepared

add.bdf
add.vwf
boxing.bsf
boxing.vhd
boxing.vhd.bak
dds.asm.rpt
dds.bdf
dds.done
dds.dpf
dds.fit.rpt
dds.fit.smsg
dds.fit.summary
dds.flow.rpt
dds.jdi
dds.jpg
dds.map.rpt
dds.map.summary
dds.merge.rpt
dds.pin
dds.qpf
dds.qsf
dds.sim.rpt
dds.sof
dds.sta.rpt
dds.sta.summary
dds.stp
dds_assignment_defaults.qdf
dds1_dds.txt
dss.vwf
fctl.bsf
fctl.vhd
fctl.vhd.bak
fenpin.bsf
fenpin.vhd
fenpin.vhd.bak
fenpin.vwf
lpm_rom0.bsf
lpm_rom0.cmp
lpm_rom0.qip
lpm_rom0.vhd
lpm_rom0_wave0.jpg
lpm_rom0_waveforms.html
rom_data.hex
serv_req_info.txt
tb2_ie_info.xml
wctl.bsf
wctl.vhd
wctl.vhd.bak

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