VHDL-FPGA-Verilog List Page 1324

VHDL-FPGA-Verilog list

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shumaguandongtaixianshi Downloaded：0: Development board 8 digital tube dynamic display from 0 to 7. Through this experiment, master the 7-segment LED display decoder and digital tube dynamic scan display method using Verilog HDL language programming.
Date : 2025-08-28 Size : 448kb User : 王恒
PWMkongzhiLEDxianshi Downloaded：0: PWM output to control LED display. Through this experiment, master PWM output to control LED display as well as the works of the PWM control using Verilog HDL language programming.
Date : 2025-08-28 Size : 439kb User : 王恒
anjianxiaochudoudongkongzhiLED Downloaded：0: Buttons control the LED light off. Through this experiment, master Verilog HDL language programming buttons control the LED lights off and the key debounce.
Date : 2025-08-28 Size : 442kb User : 王恒
LEDshanshuodeng Downloaded：0: The experimental board 8 LED periodically flashes. Through this experiment, the familiar and the master counts and judgment to achieve the Verilog HDL programming methods divide as well as the use of Quartus II software
Date : 2025-08-28 Size : 443kb User : 王恒
duquanjianxinhao Downloaded：0: Eight button control panel through the development of light-emitting diode led1 ~ led8. Through this experiment, and further understand the case statement programming and FPGA I/O port output control.
Date : 2025-08-28 Size : 434kb User : 王恒
fft Downloaded：0: the zip file includes the material including vhdl coding basics. these will be very helpful to a basic programmer.
Date : 2025-08-28 Size : 1.46mb User : lakshman
The-key-control-divider Downloaded：0: This a use of the VHDL code written by key control divider divider output through to key s3, s2, s1, s0 endowed different values, different frequencies, this code is the original for homemade oscilloscope divider.
Date : 2025-08-28 Size : 6kb User : yubaoming
scanled Downloaded：0: The FPGA system circuit control 8 LED status of the four operating modes cycle through four operating modes state: (1) from left to right by-lit LED (2) from right to left, one by one lit LED (3 ) one by one from both si
Date : 2025-08-28 Size : 569kb User : yubaoming
3-seconds-alarm Downloaded：0: This a use of language vhdl fpga program can realize alarm functionality of three seconds.
Date : 2025-08-28 Size : 324kb User : yubaoming
adc0809 Downloaded：0: This a use of language vhdl fpga program it to analog voltage signal by the digital display.
Date : 2025-08-28 Size : 382kb User : yubaoming
cnt10 Downloaded：0: This a use of the VHDL language fpga code, it can achieve the 0-9 count.
Date : 2025-08-28 Size : 1.52mb User : yubaoming
sopcAD7352nios Downloaded：0: The sopc 7352 AD module nios soft core multichannel write. Rar
Date : 2025-08-28 Size : 18.9mb User : hnbcyrnd89

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