FPGA implementation of the UART, engineering and design documentation for instructions

UART的FPGA实现\uart.qpf
..............\uart.qsf
..............\uart_description.txt
..............\uart.map.smsg
..............\uart.map.summary
..............\uart.pin
..............\uart.fit.smsg
..............\uart.fit.summary
..............\uart.sof
..............\uart.pof
..............\uart.tan.summary
..............\uart.done
..............\uart.dpf
..............\uart.cdf
..............\top.bsf
..............\src\txd.v
..............\...\uart.v
..............\...\divider.v
..............\...\ebi.v
..............\...\rxd.v
..............\...\top.v
..............\testbench\vsim_stacktrace.vstf
..............\.........\transcript
..............\.........\vish_stacktrace.vstf
..............\.........\top_tb.v
..............\.........\ModelSim.jpg
..............\.........\tcl_stacktrace.txt
..............\.........\vsim.wlf
..............\.........\uart.mpf
..............\.........\uart.cr.mti
..............\.........\cycloneII_v\_info
..............\.........\work\_info
..............\.........\....\uart\_primary.vhd
..............\.........\....\....\_primary.dat
..............\.........\....\....\verilog.asm
..............\.........\....\rxd\_primary.vhd
..............\.........\....\...\_primary.dat
..............\.........\....\...\verilog.asm
..............\.........\....\txd\_primary.vhd
..............\.........\....\...\_primary.dat
..............\.........\....\...\verilog.asm
..............\.........\....\.op\_primary.vhd
..............\.........\....\...\_primary.dat
..............\.........\....\...\verilog.asm
..............\.........\....\ebi\_primary.vhd
..............\.........\....\...\_primary.dat
..............\.........\....\...\verilog.asm
..............\.........\....\division\_primary.vhd
..............\.........\....\........\_primary.dat
..............\.........\....\........\verilog.asm
..............\.........\....\....der\_primary.vhd
..............\.........\....\.......\_primary.dat
..............\.........\....\.......\verilog.asm
..............\.........\....\top_tb\_primary.vhd
..............\.........\....\......\_primary.dat
..............\.........\....\......\verilog.asm
..............\uart.map.rpt
..............\uart.fit.rpt
..............\uart.asm.rpt
..............\uart.tan.rpt
..............\uart.flow.rpt
..............\uart.qws
..............\UART设计文档.pdf
..............\testbench\work\uart
..............\.........\....\rxd
..............\.........\....\txd
..............\.........\....\top
..............\.........\....\ebi
..............\.........\....\division
..............\.........\....\divider
..............\.........\....\top_tb
..............\.........\....\_temp
..............\.........\cycloneII_v
..............\.........\work
..............\src
..............\testbench
..............\db
UART的FPGA实现

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