VHDL-FPGA-Verilog List Page 1277

VHDL-FPGA-Verilog list

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ddr-sdram Downloaded：0: It is complete document for DDR SD RAM program in verilog hdl
Date : 2025-08-26 Size : 876kb User : srikanth
CPU_Sinple Downloaded：0: Function joint completely designed in accordance with the design of the various components to achieve single-cycle CPU to CPU.
Date : 2025-08-26 Size : 10.5mb User : 贺俊杰
zhangxing Downloaded：0: Digital alarm clock, clock and alarm functions
Date : 2025-08-26 Size : 480kb User : 张迪
SPI_DAC Downloaded：0: adc saprtan 3e starter kit
Date : 2025-08-26 Size : 12kb User : cel
uart_tx1 Downloaded：0: UART TX spartan 3e starter kit
Date : 2025-08-26 Size : 1.14mb User : cel
universal_shift_register Downloaded：0: universal shift register spartan 3e
Date : 2025-08-26 Size : 744kb User : cel
uart_rx Downloaded：0: UART RX spartan 3e starter kit
Date : 2025-08-26 Size : 178kb User : cel
sumador_punto_flotante Downloaded：0: float point adder spartan 3e
Date : 2025-08-26 Size : 483kb User : cel
FFT_16point Downloaded：0: this is 16 point vhdl code.
Date : 2025-08-26 Size : 58kb User : changho yim
cnttest Downloaded：0: this is counter vhdl code.
Date : 2025-08-26 Size : 6kb User : changho yim
MySD_Card Downloaded：0: verilog language
Date : 2025-08-26 Size : 4.45mb User : 柳霖风
Bai1.5 Downloaded：0: Code example for verilog FPGA
Date : 2025-08-26 Size : 22kb User : dotana

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