VHDL-FPGA-Verilog List Page 1281

VHDL-FPGA-Verilog list

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VHDL_FIR Downloaded：0: VHDL design of the 14-order FIR filter design, according to the filter coefficients as well as the verification process has been given the EP2S60F484C3 selected Altera devices.
Date : 2025-08-26 Size : 185kb User : 张雷
DDS Downloaded：0: A DDS program is useful, can produce controllable frequency sine wave
Date : 2025-08-26 Size : 1.97mb User : Engr.Echo
decoder83 Downloaded：0: A 83 decoder
Date : 2025-08-26 Size : 273kb User : Engr.Echo
freq_meter Downloaded：0: Frequency counter using verilog write switch stalls
Date : 2025-08-26 Size : 1.19mb User : Engr.Echo
FinalCPU Downloaded：0: a simple CPU program writen by VHDL language , it realizes the add, subtract, multiply ，divide and shift function.
Date : 2025-08-26 Size : 471kb User : myw
M_code Downloaded：0: m code
Date : 2025-08-26 Size : 152kb User : uodsi
dds Downloaded：0: The vhdl language written dds part of the code , to stay , convenient View
Date : 2025-08-26 Size : 2kb User : 郑
ISE_lab14 Downloaded：0: Xilinx company s previous software FPGA experimental program
Date : 2025-08-26 Size : 507kb User : 郑
ISE_lab15 Downloaded：0: FPGA experimental program xilinx company s previous software
Date : 2025-08-26 Size : 1.97mb User : 郑
ISE_lab16 Downloaded：0: FPGA experimental program xilinx company s previous software
Date : 2025-08-26 Size : 472kb User : 郑
ISE_lab17 Downloaded：0: FPGA experimental program xilinx company s previous software
Date : 2025-08-26 Size : 2.57mb User : 郑
ISE_lab18 Downloaded：0: FPGA experimental program xilinx company s previous software
Date : 2025-08-26 Size : 4.67mb User : 郑

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