VHDL-FPGA-Verilog List Page 1282

VHDL-FPGA-Verilog list

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led Downloaded：0: Design of light water
Date : 2025-08-26 Size : 568kb User : 冯丽洋
lcd Downloaded：0: To achieve ICD display, run in ISE8.2 chip xinlix the virtex4
Date : 2025-08-26 Size : 767kb User : 冯丽洋
key Downloaded：0: Key operation run in ISE8.2 chip xinlix the virtex4
Date : 2025-08-26 Size : 503kb User : 冯丽洋
parall_ad_da Downloaded：0: Achieve ad_da, running in ISE8.2 chip for xinlix the virtex4
Date : 2025-08-26 Size : 883kb User : 冯丽洋
serial_adda Downloaded：0: To achieve serial port, ISE8.2 running chip for xinlix the virtex4
Date : 2025-08-26 Size : 789kb User : 冯丽洋
trajectory_planning_2011_11_09 Downloaded：0: The use of the FPGA, create NIOS2 processor, inverse kinematics, trajectory planning, the the ALTERA hurricane 2 processor, the processing speed is very fast
Date : 2025-08-26 Size : 5.34mb User : 沙佑平
encoder Downloaded：0: Eight priority encoder, write code using FPGA using ALTERA hurricane processor, code runs faster, verify that no errors
Date : 2025-08-26 Size : 252kb User : 沙佑平
e1framerdeframer Downloaded：0: E1 Framer deframer
Date : 2025-08-26 Size : 35kb User : lijunwen
lab1 Downloaded：0: xilinx spartan-3eEDK Experiment 1 source
Date : 2025-08-26 Size : 3.54mb User : 李炳
VHDL_SDH Downloaded：0: VHDL source code of modern fiber-optic communication SDH the SDH overhead of receiving and processing.
Date : 2025-08-26 Size : 56kb User : 张雷
VHDL_LAPS Downloaded：0: Simplify LAPS protocol, encapsulation, transmission, and receiving the transmitted data packet, containing FCS is performed on the entire LAPS frame CRC.
Date : 2025-08-26 Size : 160kb User : 张雷
VHDL_Ethernet Downloaded：0: VHDL realization of Ethernet test instrument can generate a variety of modes depending on the configuration of Ethernet data packets, and receives Ethernet data statistics.
Date : 2025-08-26 Size : 259kb User : 张雷

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