VHDL-FPGA-Verilog List Page 1286

VHDL-FPGA-Verilog list

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chap3 Downloaded：0: this is code about FPGA
Date : 2025-08-27 Size : 6kb User : zhangxiao
chap11 Downloaded：0: This the book depth Fun FPGA FPGA section XI of experimental code can refer to the privileged students learning
Date : 2025-08-27 Size : 5kb User : zhangxiao
MonitorB Downloaded：0: VHDL write a monitoring system, including the shaping of information, serial-to-parallel conversion and parity status judgment, the judgment of the information format monitor
Date : 2025-08-27 Size : 776kb User : xiaok
led_keyscan Downloaded：0: verilog file micro key DIP switch detection code
Date : 2025-08-27 Size : 1kb User : 盛瑞
BCD-youxianbianma Downloaded：1: Priority encoder BCD priority encoder function through VHDL language
Date : 2025-08-27 Size : 1kb User : victor
BCD-counter Downloaded：1: A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clo
Date : 2025-08-27 Size : 1kb User : victor
shift-register Downloaded：1: An 8-bit left and right shift register circuit, the input of the clock signal CLK, the direction control signal D, the output signal of the status of each register.
Date : 2025-08-27 Size : 1kb User : victor
clock Downloaded：1: A clock distribution circuit, the input clock signal CLK, the output signal F0 ~~ F5, the six signal only allowed to have a high level, F0, F2, F4 duration of two CLK, F1, F3, F5 duration of four CLK.
Date : 2025-08-27 Size : 1kb User : victor
motor Downloaded：1: The state machine circuit, the driving of the stepping motor, the four-phase control coils A, B, and C, and D. The motor forward four-phase control coil is energized procedure: A-AB-B-BC-C-CD-D-DA-A ..., the backward pro
Date : 2025-08-27 Size : 1kb User : victor
EDAjiaotong Downloaded：0: EDA red yellow and green traffic lights turn left, four different times, there is a timer
Date : 2025-08-27 Size : 824kb User : fyhsam
duogongnengzhong Downloaded：0: Adjustable multi-functional digital clock time, calibration time, date, alarm clock
Date : 2025-08-27 Size : 595kb User : fyhsam
VHDL-program Downloaded：0: Program VHDL experiment. Need can be modified on this basis.
Date : 2025-08-27 Size : 11.22mb User : 梁康

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