Function joint completely designed in accordance with the design of the various components to achieve single-cycle CPU to CPU.

CPU_Sinple\aandb.v
..........\aandbbit.v
..........\adder.v
..........\adder.v.bak
..........\addersp.v
..........\alu.v
..........\alu.v.bak
..........\ALU_Controller.v
..........\aorb.v
..........\aorbbit.v
..........\axorb.v
..........\axorbbit.v
..........\choose1or0.v
..........\choosebit.v
..........\chose.v
..........\chose32bits.v
..........\chose5bits.v
..........\cpucontroller.v
..........\cpucontroller.v.bak
..........\CPU_Sinple.asm.rpt
..........\CPU_Sinple.done
..........\CPU_Sinple.fit.rpt
..........\CPU_Sinple.fit.smsg
..........\CPU_Sinple.fit.summary
..........\CPU_Sinple.flow.rpt
..........\CPU_Sinple.map.rpt
..........\CPU_Sinple.map.smsg
..........\CPU_Sinple.map.summary
..........\CPU_Sinple.pin
..........\CPU_Sinple.pof
..........\CPU_Sinple.qpf
..........\CPU_Sinple.qsf
..........\CPU_Sinple.qws
..........\CPU_Sinple.sdc
..........\CPU_Sinple.sim.rpt
..........\CPU_Sinple.sof
..........\CPU_Sinple.sta.rpt
..........\CPU_Sinple.sta.summary
..........\CPU_Sinple.tan.rpt
..........\CPU_Sinple.tan.summary
..........\CPU_Sinple.v
..........\CPU_Sinple.v.bak
..........\CPU_Sinple.vwf
..........\datastorage.v
..........\.b\CPU_Sinple.asm.qmsg
..........\..\CPU_Sinple.asm_labs.ddb
..........\..\CPU_Sinple.cbx.xml
..........\..\CPU_Sinple.cmp.bpm
..........\..\CPU_Sinple.cmp.cdb
..........\..\CPU_Sinple.cmp.ecobp
..........\..\CPU_Sinple.cmp.hdb
..........\..\CPU_Sinple.cmp.kpt
..........\..\CPU_Sinple.cmp.logdb
..........\..\CPU_Sinple.cmp.rdb
..........\..\CPU_Sinple.cmp.tdb
..........\..\CPU_Sinple.cmp0.ddb
..........\..\CPU_Sinple.cmp_merge.kpt
..........\..\CPU_Sinple.db_info
..........\..\CPU_Sinple.eco.cdb
..........\..\CPU_Sinple.eds_overflow
..........\..\CPU_Sinple.fit.qmsg
..........\..\CPU_Sinple.fnsim.cdb
..........\..\CPU_Sinple.fnsim.hdb
..........\..\CPU_Sinple.fnsim.qmsg
..........\..\CPU_Sinple.hier_info
..........\..\CPU_Sinple.hif
..........\..\CPU_Sinple.lpc.html
..........\..\CPU_Sinple.lpc.rdb
..........\..\CPU_Sinple.lpc.txt
..........\..\CPU_Sinple.map.bpm
..........\..\CPU_Sinple.map.cdb
..........\..\CPU_Sinple.map.ecobp
..........\..\CPU_Sinple.map.hdb
..........\..\CPU_Sinple.map.kpt
..........\..\CPU_Sinple.map.logdb
..........\..\CPU_Sinple.map.qmsg
..........\..\CPU_Sinple.map_bb.cdb
..........\..\CPU_Sinple.map_bb.hdb
..........\..\CPU_Sinple.map_bb.logdb
..........\..\CPU_Sinple.pre_map.cdb
..........\..\CPU_Sinple.pre_map.hdb
..........\..\CPU_Sinple.ram0_register_ea496d89.hdl.mif
..........\..\CPU_Sinple.rtlv.hdb
..........\..\CPU_Sinple.rtlv_sg.cdb
..........\..\CPU_Sinple.rtlv_sg_swap.cdb
..........\..\CPU_Sinple.sgdiff.cdb
..........\..\CPU_Sinple.sgdiff.hdb
..........\..\CPU_Sinple.sim.cvwf
..........\..\CPU_Sinple.sim.hdb
..........\..\CPU_Sinple.sim.qmsg
..........\..\CPU_Sinple.sim.rdb
..........\..\CPU_Sinple.simfam
..........\..\CPU_Sinple.sld_design_entry.sci
..........\..\CPU_Sinple.sld_design_entry_dsc.sci
..........\..\CPU_Sinple.syn_hier_info
..........\..\CPU_Sinple.tan.qmsg
..........\..\CPU_Sinple.tis_db_list.ddb
..........\..\CPU_Sinple.tmw_info
..........\..\CPU_Sinple_global_asgn_op.abo
..........\..\mux_3nc.tdf

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