VHDL-FPGA-Verilog List Page 1273

VHDL-FPGA-Verilog list

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grlib-gpl-1.1.0-b4113 Downloaded：0: gaisler developers can use for free ip collection, many of us used the ip code where you can find.
Date : 2025-08-26 Size : 24.05mb User : jiangxingtong
counter Downloaded：0: 50MHz clock signal at a frequency of 1Hz, to count the 1 Hz square wave signal, and using 4 Siamese digital tube dynamic display
Date : 2025-08-26 Size : 1kb User : 君君
shiyan2 Downloaded：0: Serial port to send data transmitted via DIP switch, and send data in digital display
Date : 2025-08-26 Size : 4kb User : 君君
spi_master_slave Downloaded：0: Synchronous serial data transmission the SPI--s source code, it can be configured as host or slave, hanging on a bus.
Date : 2025-08-26 Size : 646kb User : jiangxingtong
dma_ahb Downloaded：0: Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.
Date : 2025-08-26 Size : 733kb User : jiangxingtong
ultimate_crc_latest.tar Downloaded：0: CRC Cyclic check source code from the OPENCOREs, the error checking used in the digital circuit.
Date : 2025-08-26 Size : 226kb User : jiangxingtong
bch_dec_enc_dcd_latest.tar Downloaded：0: The BCH decoder design source code, it can achieve the two error correction. This is the latest version.
Date : 2025-08-26 Size : 1016kb User : jiangxingtong
digital-clock Downloaded：0: Digital clock, LED indicates the seconds, four digital display hours and minutes before the whole point of the LED 8 flashing instead of the buzzer timekeeping
Date : 2025-08-26 Size : 6kb User : 白狼
VHDL-Handbook Downloaded：0: vhdl handbook
Date : 2025-08-26 Size : 1.28mb User : 健康路
error_injector_test Downloaded：0: This a vhdl code for error injection code for colour converter fpga program
Date : 2025-08-26 Size : 2kb User : usha
register_test Downloaded：0: This a vhdl code for tseting the colour gen code for fpga
Date : 2025-08-26 Size : 1kb User : usha
lesson1 Downloaded：0: eda learning files
Date : 2025-08-26 Size : 105kb User : 健康路

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