VHDL-FPGA-Verilog List Page 1271

VHDL-FPGA-Verilog list

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divisor_frecuencia Downloaded：0: its a divider clock. its possible select the frequency based in a master clock
Date : 2025-08-26 Size : 1kb User : edgar
ffjk Downloaded：0: its a flip flop jk based in quartus II altera
Date : 2025-08-26 Size : 248kb User : edgar
Comparador Downloaded：0: its a comparator of 4bits with ins cascade
Date : 2025-08-26 Size : 1.01mb User : edgar
Four-Consecutive-Ones-Detector Downloaded：0: its a counter of four ones consecutive
Date : 2025-08-26 Size : 142kb User : edgar
Quadruple-2-Input-Exclusive-Or-Gates Downloaded：0: quadruple dual input exclusive or gates
Date : 2025-08-26 Size : 86kb User : edgar
counter60 Downloaded：0: Experimental plate to achieve mode 60 counts, namely 00-01-02-03-04- ... 59-00-01 ... AN1 ~ AN0 Basys2 experiment board with (LD7 ~ LD0).
Date : 2025-08-26 Size : 283kb User : veryshi
shuzizhong Downloaded：0: Digital clock verilog program, school, alarm clock correction, the whole point timekeeping function.
Date : 2025-08-26 Size : 100kb User : veryshi
dianji Downloaded：0: The design of the integrated monitoring and control system of the DC motor, DC motor drive control circuit top-level design
Date : 2025-08-26 Size : 394kb User : lou
zhengxian Downloaded：0: verilog sine function signal generator design. Can generate a different signal waveform of the sine function.
Date : 2025-08-26 Size : 898kb User : lou
mokekong Downloaded：0: Mold controllable counter design, top-level document, simulation files, and so on.
Date : 2025-08-26 Size : 1.5mb User : lou
vgaxianshi Downloaded：0: Based on Verilog language VGA display circuit design file, the top-level design file
Date : 2025-08-26 Size : 804kb User : lou
pingpang Downloaded：0: Game of table tennis circuit VGA display, the program has been designed, can be altered
Date : 2025-08-26 Size : 1.73mb User : lou

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