VHDL-FPGA-Verilog List Page 1268

VHDL-FPGA-Verilog list

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miaobiao Downloaded：0: It has a timer function. This stopwatch has two buttons (reset, start) reset button is pressed, the stopwatch is cleared, press the start key, start the timer, press the start key again, pause timing, stopwatch display f
Date : 2025-08-26 Size : 1.3mb User : 张远辉
clk_dly Downloaded：0: choose a person for a job； make use of personnel； need hands
Date : 2025-08-26 Size : 1kb User : 李文
jtd Downloaded：0: Crossroads traffic light control system, LED light-emitting diode on the experimental platform to display the vehicle direction (east-west and north-south through the group), the direction of the remaining time with digi
Date : 2025-08-26 Size : 492kb User : 黄黄
xinhao Downloaded：0: Simple signal generator can output three waveforms, incremental sawtooth generator module, the sine wave generator module, a square wave generator module, waveform selector module, vhdl
Date : 2025-08-26 Size : 59kb User : 沈微
VGA Downloaded：0: Through its programming output RGB trichromatic signals and synchronization signals HS, VS line field scanning. CPLD to accept the the microcontroller output of control signals, internal data selector module based on the
Date : 2025-08-26 Size : 3kb User : 苗静
Part- Downloaded：0: data transfer from one multiport ram top other multi port ram. it is a system generator compatible bile
Date : 2025-08-26 Size : 22kb User : prince
pci-express-system-architecture.pdf.tar Downloaded：0: PCI Express is a high performance, general purpose Serial I/O Interconnect defined for a wide variety of future computing and communication platforms. The basic premise of PCI Express is that the host PCI software remain
Date : 2025-08-26 Size : 4.42mb User : mahavir
sv_mux.tar Downloaded：0: it is the verification code written in system verilog for the verification of 4:1 mux and with functional coverage
Date : 2025-08-26 Size : 3kb User : mahavir
mux_ovm_full-cover.tar Downloaded：0: this 4:1 mux verification code which is written in ovm and with functional coverage
Date : 2025-08-26 Size : 4.29mb User : mahavir
pci_express.pdf.tar Downloaded：0: in this pdf the internal architecture of pci has explained. e.g. transaction layer data link layer ,physical layer
Date : 2025-08-26 Size : 489kb User : mahavir
make-file-vcs.tar Downloaded：0: this the verilog code of 4:1 mux and i have used case statement to explain the logic of this mux
Date : 2025-08-26 Size : 1kb User : mahavir
LineBuffer---shifttaps Downloaded：0: Line Buffer。rar
Date : 2025-08-26 Size : 2kb User : adamusi

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