VHDL-FPGA-Verilog List Page 1264

VHDL-FPGA-Verilog list

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FPGAPCI Downloaded：0: FPGA PCI板卡原理图 FPGA PCI板卡原理图
Date : 2025-08-26 Size : 751kb User : tyc
preambledeassemble Downloaded：0: its useful for dissembler data from continuous stream of transmitter data stream
Date : 2025-08-26 Size : 1kb User : kishan patel
costable.zip Downloaded：0: cos_table main application in the GPS receiver, through the programming of the quartus9.1 implementation, control the received program
Date : 2025-08-26 Size : 7kb User : cc
frequency_lms.zip Downloaded：0: Control the frequency of occurrence of the word, and change the frequency control word can be changed whether the frequency of occurrence and can change the frequency change. This procedure can be achieved, the control w
Date : 2025-08-26 Size : 2kb User : cc
SPI-desgn.zip Downloaded：0: Synchronous serial peripheral interface, it can make the MCU with a variety of peripheral devices to communicate in order to exchange information in a serial manner. The transmission of data for eight master enable signa
Date : 2025-08-26 Size : 2kb User : cc
uart_txd_rxd.zip Downloaded：0: Converting the received parallel data into serial data to transmit. The message frame from a low start bit is followed by 5 to 8 data bits, parity bit, and one of the available one or several of the high stop bit. Receiv
Date : 2025-08-26 Size : 3kb User : cc
RS232C_Verilog.rar Downloaded：0: The codes of verilog hdl for RS232C, its useful characteristic can be integrated in a big system.
Date : 2025-08-26 Size : 10kb User : huangbin
RS232C_vhdl.rar Downloaded：0: The codes of VHDL for RS232C, its useful characteristic can be integrated in a big system.
Date : 2025-08-26 Size : 105kb User : huangbin
shift Downloaded：0: " Two-way" means plus or minus 1 operation, with a statement if dir = ' 1 ' then ... to the else realization asynchronous clear " means as long as the reset is high, cleared immediately, without the nee
Date : 2025-08-26 Size : 232kb User : shuang
first Downloaded：0: The 3-8 decoder: input variables for the three A, B, C, the output variables are eight, i.e. the Y0 ~~ Y7. G1, G2A, G2B strobe input, only when G1 = 1, G2A = 0, G2b = 0, the decoder can output correctly, otherwise, the d
Date : 2025-08-26 Size : 189kb User : shuang
ASSIGNMENT3 Downloaded：0: Implementation of risc processor program in verilog coding.
Date : 2025-08-26 Size : 116kb User : poo
CBPFPGA Downloaded：0: it is good to study the FPGA
Date : 2025-08-26 Size : 1.3mb User : liuhai

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