VHDL-FPGA-Verilog List Page 1261

VHDL-FPGA-Verilog list

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Audio_DAC_FIFO Downloaded：0: terasic the DM9000A module source, use nios2 do Ethernet applications should be used
Date : 2025-08-26 Size : 15kb User : llwww
PWM_OUT Downloaded：0: This is a PWM signal to control the brightness of the LED to the LED source a EP2C5T144 the FPGA button to change the duty cycle, with the circuit diagram :)
Date : 2025-08-26 Size : 272kb User : 何健能
DDS Downloaded：0: This a used EP2C5T144 FPGA produced DDS signal generator, the output signal waveform variable adjustable amplitude, the disadvantage is that the signal frequency is slightly lower, with the circuit diagram
Date : 2025-08-26 Size : 1.06mb User : 何健能
bit4_4 Downloaded：0: Verilog language program control the four relay switch action RS232 communication
Date : 2025-08-26 Size : 422kb User : 张思文
chenyu--chengxu Downloaded：0: Verilog language converted to RS485 RS232 bus communication
Date : 2025-08-26 Size : 193kb User : 张思文
lbq3 Downloaded：0: Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
Date : 2025-08-26 Size : 1kb User : chen
design Downloaded：1: static timing analysis and timing paths
Date : 2025-08-26 Size : 562kb User : Raki
stepmotornios Downloaded：0: Altera SOPC系统和Nios II处理器实现的一个简单的步进电机驱动系统。
Date : 2025-08-26 Size : 366kb User : TangTang
pci Downloaded：0: PCI operation of the the PCI hard core source code, support 33.3M clock frequency to support IO mode and memory mode
Date : 2025-08-26 Size : 1kb User : lijun
KEY Downloaded：0: VHDL language to achieve scanning keyboard and display on the digital
Date : 2025-08-26 Size : 691kb User : 田天
shuzizhong Downloaded：0: Realize single-chip digital clock, hour, minute and second of the display, as well as the whole point timekeeping function.
Date : 2025-08-26 Size : 8kb User : 王军
01-USB Downloaded：0: Read usb data
Date : 2025-08-26 Size : 13.66mb User : 张亚龙

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