Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.

dma_ahb
.......\branches
.......\tags
.......\trunk
.......\.....\doc
.......\.....\...\PR201_trm_rev1.5.pdf
.......\.....\README.txt
.......\.....\src
.......\.....\...\dma_ahb32
.......\.....\...\.........\dma_ahb32.v
.......\.....\...\.........\dma_ahb32_apb_mux.v
.......\.....\...\.........\dma_ahb32_ch_reg_params.v
.......\.....\...\.........\dma_ahb32_core0.v
.......\.....\...\.........\dma_ahb32_core0_ahbm_rd.v
.......\.....\...\.........\dma_ahb32_core0_ahbm_timeout.v
.......\.....\...\.........\dma_ahb32_core0_ahbm_wr.v
.......\.....\...\.........\dma_ahb32_core0_arbiter.v
.......\.....\...\.........\dma_ahb32_core0_ch.v
.......\.....\...\.........\dma_ahb32_core0_channels.v
.......\.....\...\.........\dma_ahb32_core0_channels_apb_mux.v
.......\.....\...\.........\dma_ahb32_core0_channels_mux.v
.......\.....\...\.........\dma_ahb32_core0_ch_calc.v
.......\.....\...\.........\dma_ahb32_core0_ch_calc_addr.v
.......\.....\...\.........\dma_ahb32_core0_ch_calc_joint.v
.......\.....\...\.........\dma_ahb32_core0_ch_calc_size.v
.......\.....\...\.........\dma_ahb32_core0_ch_empty.v
.......\.....\...\.........\dma_ahb32_core0_ch_fifo.v
.......\.....\...\.........\dma_ahb32_core0_ch_fifo_ctrl.v
.......\.....\...\.........\dma_ahb32_core0_ch_fifo_ptr.v
.......\.....\...\.........\dma_ahb32_core0_ch_offsets.v
.......\.....\...\.........\dma_ahb32_core0_ch_outs.v
.......\.....\...\.........\dma_ahb32_core0_ch_periph_mux.v
.......\.....\...\.........\dma_ahb32_core0_ch_rd_slicer.v
.......\.....\...\.........\dma_ahb32_core0_ch_reg.v
.......\.....\...\.........\dma_ahb32_core0_ch_reg_size.v
.......\.....\...\.........\dma_ahb32_core0_ch_remain.v
.......\.....\...\.........\dma_ahb32_core0_ch_wr_slicer.v
.......\.....\...\.........\dma_ahb32_core0_ctrl.v
.......\.....\...\.........\dma_ahb32_core0_top.v
.......\.....\...\.........\dma_ahb32_core0_wdt.v
.......\.....\...\.........\dma_ahb32_defines.v
.......\.....\...\.........\dma_ahb32_dual_core.v
.......\.....\...\.........\dma_ahb32_reg.v
.......\.....\...\.........\dma_ahb32_reg_core0.v
.......\.....\...\.........\dma_ahb32_reg_params.v
.......\.....\...\.........\filelist.txt
.......\.....\...\.........\prgen_delay.v
.......\.....\...\.........\prgen_demux8.v
.......\.....\...\.........\prgen_fifo.v
.......\.....\...\.........\prgen_joint_stall.v
.......\.....\...\.........\prgen_min2.v
.......\.....\...\.........\prgen_min3.v
.......\.....\...\.........\prgen_mux8.v
.......\.....\...\.........\prgen_or8.v
.......\.....\...\.........\prgen_rawstat.v
.......\.....\...\.........\prgen_scatter8_1.v
.......\.....\...\.........\prgen_stall.v
.......\.....\...\.........\prgen_swap_32.v
.......\.....\...\.........\README.txt
.......\.....\...\dma_ahb64
.......\.....\...\.........\dma_ahb64.v
.......\.....\...\.........\dma_ahb64_apb_mux.v
.......\.....\...\.........\dma_ahb64_ch_reg_params.v
.......\.....\...\.........\dma_ahb64_core0.v
.......\.....\...\.........\dma_ahb64_core0_ahbm_rd.v
.......\.....\...\.........\dma_ahb64_core0_ahbm_timeout.v
.......\.....\...\.........\dma_ahb64_core0_ahbm_wr.v
.......\.....\...\.........\dma_ahb64_core0_arbiter.v
.......\.....\...\.........\dma_ahb64_core0_ch.v
.......\.....\...\.........\dma_ahb64_core0_channels.v
.......\.....\...\.........\dma_ahb64_core0_channels_apb_mux.v
.......\.....\...\.........\dma_ahb64_core0_channels_mux.v
.......\.....\...\.........\dma_ahb64_core0_ch_calc.v
.......\.....\...\.........\dma_ahb64_core0_ch_calc_addr.v
.......\.....\...\.........\dma_ahb64_core0_ch_calc_joint.v
.......\.....\...\.........\dma_ahb64_core0_ch_calc_size.v
.......\.....\...\.........\dma_ahb64_core0_ch_empty.v
.......\.....\...\.........\dma_ahb64_core0_ch_fifo.v
.......\.....\...\.........\dma_ahb64_core0_ch_fifo_ctrl.v
.......\.....\...\.........\dma_ahb64_core0_ch_fifo_ptr.v
.......\.....\...\.........\dma_ahb64_core0_ch_offsets.v
.......\.....\...\.........\dma_ahb64_core0_ch_outs.v
.......\.....\...\.........\dma_ahb64_core0_ch_periph_mux.v
.......\.....\...\.........\dma_ahb64_core0_ch_rd_slicer.v
.......\.....\...\......

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