VHDL-FPGA-Verilog List Page 1141

VHDL-FPGA-Verilog list

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Verilog-UART Downloaded：0: Verilog UART
Date : 2025-08-21 Size : 16kb User : mrmu
nios.ii Downloaded：0: NIOSII development routine source code, including SPI, DMA, PIO, etc.
Date : 2025-08-21 Size : 13.35mb User : kmtian
daima Downloaded：0: Verilog HDL
Date : 2025-08-21 Size : 141kb User : 石
barrelshift Downloaded：0: 8-bit parametric barrel shifter
Date : 2025-08-21 Size : 1kb User : Taffy
DDS Downloaded：0: DDS function, you can generate a frequency tunable, phase adjustable, adjustable amplitude of the sine wave.
Date : 2025-08-21 Size : 3.36mb User : 铁宁力
DE0_VGA Downloaded：1: Using FPGA design game design, live-action version of Super Mario, VGA display
Date : 2025-08-21 Size : 310kb User : limin
ALU Downloaded：0: 8-bit unsigned, 16 operations(arithmetic and logic).
Date : 2025-08-21 Size : 1kb User : Taffy
Shifter Downloaded：0: Modified 4-bit SISO shift register. Reset value 1101.
Date : 2025-08-21 Size : 2kb User : Taffy
RISC-CPU Downloaded：1: RISC CPU properly verified by simulation (using the previously sure to see the readme file and structure chart!) This CPU is the last chapter Xia Wen verilog Digital System Design Guide routine. 2 study sure to thoroughl
Date : 2025-08-21 Size : 4.14mb User : 刘栋
LED_RUN Downloaded：0: 8 bit Verilog code design---- QUATUS II-based development environment, using Verilog code entry students
Date : 2025-08-21 Size : 93kb User : zhukunshun
chaoqianadd6 Downloaded：0: Adder VHDL design ahead of six, six binary addition operation.
Date : 2025-08-21 Size : 1kb User : 陈峰
chufa Downloaded：0: Four divider with VHDL design, you can achieve the four binary division operation
Date : 2025-08-21 Size : 1kb User : 陈峰

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