VHDL-FPGA-Verilog List Page 1145

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .40 .41 .42 .43 .44 1145.46 .47 .48 .49 .50 ... 4310 »

jiaotongdeng Downloaded：0: Traffic signal controller, can be downloaded to the FPGA development board, automatic traffic light control procedures, written by VHDL environment QUTUS2
Date : 2025-08-21 Size : 1.72mb User : dengnana
EDA-Clock Downloaded：0: Basic functions: input 1kHz clock 2, display hours, minutes, seconds, 24-hour clock 3, hour and minute correction function 4, when the timer runs to 59 minutes 49 seconds timekeeping, each tweet 1s stopped called 1s reso
Date : 2025-08-21 Size : 371kb User : 李伟
uart_Verilog Downloaded：0: Verilog-based RS232 serial communication experiment, 256-bit data can be sent on Altera' s EP4CE15F17C8 chip authentication is successful.
Date : 2025-08-21 Size : 4.6mb User : xuxinchuan
uart_state Downloaded：0: Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verify on Altera' s EP4CE15F17C8 chip. (Sent with another 256 different
Date : 2025-08-21 Size : 3.16mb User : xuxinchuan
lcd_spi Downloaded：0: LCD12864 LCD FPGA (EP4CE15F17C8) driver experimental use the SPI serial transmission of data, display the specified image.
Date : 2025-08-21 Size : 3.58mb User : xuxinchuan
09_vga Downloaded：0: VGA driver based the FPGA (EP4CE15F17C8) experiment, the programming language for the Verilog HDL for Verilog Programming learning portal.
Date : 2025-08-21 Size : 16.92mb User : xuxinchuan
vga Downloaded：0: A VHDL VGA display, set the resolution to 640* 480, the program is very simple, for reference only.
Date : 2025-08-21 Size : 1kb User : 李国庆
TEST-CPU-2 Downloaded：0: VHDL language based on the microinstruction control of the CPU, 16-bit address lines
Date : 2025-08-21 Size : 3.08mb User : Zhiheng Shen
DE1_synthesizer Downloaded：0: DE1 music synthesizer
Date : 2025-08-21 Size : 1.15mb User : suvdantsetseg
Verilog-HDL-huawei-rumen Downloaded：0: Verilog Huawei entry information, I hope we can bring a small harvest
Date : 2025-08-21 Size : 257kb User : 吴佳琪
Washer Downloaded：0: VHDL code based on the washing machine, based on Altera' s Quartus variation completed, can be fired into the FPGA
Date : 2025-08-21 Size : 1.78mb User : Zhiheng Shen
bingzhuanchuan Downloaded：0: Serial to parallel algorithm
Date : 2025-08-21 Size : 351kb User : 王萌

« 1 2 ... .40 .41 .42 .43 .44 1145.46 .47 .48 .49 .50 ... 4310 »

Search in result