VHDL-FPGA-Verilog List Page 1146

VHDL-FPGA-Verilog list

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7.2_MidFilter Downloaded：0: Based on SystemGenerator the image median filtering works successfully on the XilinxFPGA verification.
Date : 2025-08-21 Size : 117kb User : Justin Bieber
7.3_ImageSharp Downloaded：0: The image sharpening works based SystemGenerator success on the XilinxFPGA.
Date : 2025-08-21 Size : 1.24mb User : Justin Bieber
ImageEdgeDetec Downloaded：0: Three detection modes Sobel, Laplace and Gauss-Laplace operator image edge detection based on SystemGenerator. Success in XilinxFPGA verify with netlist.
Date : 2025-08-21 Size : 4.64mb User : Justin Bieber
ImageDivision Downloaded：0: Based on the image segmentation SystemGenerator, success on the XilinxFPGA verified with the netlist.
Date : 2025-08-21 Size : 3.84mb User : Justin Bieber
NCO_Test Downloaded：0: Code NCO module communication the simulation, based QUARTUSII9.0 software, code compiled successfully, and the functional simulation has been achieved
Date : 2025-08-21 Size : 1.45mb User : 二妮子
yuyin_jiami Downloaded：0: Based on quarusII simulation software, modular design, designed to meet the incoming voice signal is encrypted
Date : 2025-08-21 Size : 6.26mb User : 二妮子
sin_10k Downloaded：0: Query based on the the FPGA use of rom generate a frequency of 10 kHz sin signal, compiled successfully and to achieve functional simulation.
Date : 2025-08-21 Size : 714kb User : 二妮子
fir Downloaded：0: FPGA-based low-pass filter design, the simulation environment QuartusII9.0. The signal is low-pass filtering, the programming was successful. We hope to help
Date : 2025-08-21 Size : 335kb User : 二妮子
decoder3_8 Downloaded：0: Yanshan University VHDL curriculum design, 3-8 decoder simple code.
Date : 2025-08-21 Size : 132kb User : hanmin
jiaotongden Downloaded：0: Communication Engineering, Yanshan University VHDL curriculum design, simple traffic light programming code.
Date : 2025-08-21 Size : 197kb User : hanmin
step-machine Downloaded：0: FPGA curriculum design stepper motor simple programming code, VHDL language.
Date : 2025-08-21 Size : 118kb User : hanmin
spi-verilog Downloaded：0: SPI interface circuit is implemented in Verilog logic between master and slave processor communication
Date : 2025-08-21 Size : 15kb User : sadgfasdgi

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