VHDL-FPGA-Verilog List Page 1151

VHDL-FPGA-Verilog list

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traffic_lights Downloaded：0:  traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control  When
Date : 2025-08-21 Size : 1kb User : 吴胜兵
wwww Downloaded：0: The entire circuit is controlled by a single beverage circuit the module binctr.vhd and the the top circuit module refill.vhd composition wherein the top-level circuit module contains a control circuit of the two drinks,
Date : 2025-08-21 Size : 17kb User : 吴胜兵
car_count Downloaded：0: car_enter, car_exit vehicles entering the car park and leave the car park. count1 and count2 two counters count the number of vehicles entering the parking lot and leave the parking lot of the number of vehicles. total =
Date : 2025-08-21 Size : 392kb User : 吴胜兵
mps- Downloaded：0: 1. The pseudo-random sequence Overview, pseudo-random sequence plays a very crucial role in the spread spectrum communication system. Obtained in a direct sequence spread spectrum system transmitting end, a pseudo-random
Date : 2025-08-21 Size : 276kb User : 吴胜兵
bidirection_reg Downloaded：0: Shift register design the entire circuit is completed by a master timing process each rising edge of the clock, according to the value of the mode [1:0] is cleared, the left or right to operate in the master timing proce
Date : 2025-08-21 Size : 388kb User : 吴胜兵
p_in_s_out Downloaded：0: String into a register Design  datain [7 .. 0] is the eight-bit data input terminal, parallel input  CLK pulse input terminal, the data shift rely on this pin trigger  load the control terminal of th
Date : 2025-08-21 Size : 305kb User : 吴胜兵
digital-colok Downloaded：0: With written in VHDL quartusII code, the output is the digital clock is displayed on the board, you can also reset, and the time.
Date : 2025-08-21 Size : 9.87mb User :
add-8 Downloaded：0: Eight adder logic development source code, Coding eight adder Quartus software.
Date : 2025-08-21 Size : 164kb User :
Pld-based-VGA-display Downloaded：0: Pld-based VGA display
Date : 2025-08-21 Size : 881kb User : 郑惠文
Experiment Downloaded：0: VHDL 3-8 priority encoder decoder
Date : 2025-08-21 Size : 54kb User : alex
4-bit-Multiplier Downloaded：0: IT is a 4 bit multiplier vhdl coding file which is run in altera quatrs - II. in which 4 binary bit is multiplied and waveform can be obtained
Date : 2025-08-21 Size : 46kb User : Henal patel
WORK4 Downloaded：0: 8-3 priority encoder decoder
Date : 2025-08-21 Size : 66kb User : alex

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