VHDL-FPGA-Verilog List Page 1154

VHDL-FPGA-Verilog list

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ADS830 Downloaded：1: Amplitude-frequency equalization of digital filter design, ad830 input, 800 order of FIR filter, using DA output resistance network, the effect is very good
Date : 2025-08-21 Size : 18.12mb User : 十禅
Eight-cpu-design Downloaded：0: Microinstruction translation of the design of the output register of the unit circuit design and choice of components arithmetic component design design instruction register of the register bank design program counter ci
Date : 2025-08-21 Size : 481kb User : 直树
FILTER Downloaded：0: A working frequency (sampling frequency) 100M, cutoff frequency 10M FIR filter, a total of 108 bands. A total of four documents, the the the filter implementation file FILTER.v test platform FILTER_TB, test vectors gener
Date : 2025-08-21 Size : 10kb User : 李佩逸
led-fiash Downloaded：0: Xilinx simulation, and downloaded to the development board to achieve the operation of the LED light tube, and can be adjusted according to the procedures in the order as well as the speed of the light-emitting
Date : 2025-08-21 Size : 1kb User : 沈攀
Answer-devices Downloaded：0: Responder, two people Responder, respectively, with the button P1, P2 (P1 corresponding button S3, P2 corresponding button S4) shows a bright light that lit D3 when the button is pressed, the same button to 2:00 bright l
Date : 2025-08-21 Size : 8kb User : 沈攀
autosale Downloaded：0: Vending machines, the cargo information storage, process control, coin handling, balance calculation, display and other functions- Description: display the amount of money the value of the coin 50 cents
Date : 2025-08-21 Size : 13kb User : 沈攀
digital-frequence Downloaded：0: Digital frequency meter with four automatically according to the result of seven decimal counting, automatic selection of effective data- Description: four high dynamic display. The results shown is a digital display of
Date : 2025-08-21 Size : 18kb User : 沈攀
secret-lock Downloaded：0: Password lock four and seven: Enter the four-digit hexadecimal password incorrectly three times the police - password is four four of the input state of password settings, and P3 is pressed input password storage spaces
Date : 2025-08-21 Size : 11kb User : 沈攀
IDE_VHDL Downloaded：0: This VHDL codes with threr versions implemented IDE host protocol，supporting with UDMA。
Date : 2025-08-21 Size : 537kb User : CHEN KANG
vhdl-code Downloaded：0: VHDL component source code routines
Date : 2025-08-21 Size : 111kb User : zc
FPGA-examples Downloaded：0: FPGA instance of collection, as a programming reference, with LED, modem program
Date : 2025-08-21 Size : 240kb User : zc
Xilinx_vga_games_design Downloaded：0: Classic procedures, written in VHDL game, Tetris, on the board of the Xilinx Spartan test
Date : 2025-08-21 Size : 194kb User : zc

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