VHDL-FPGA-Verilog List Page 1158

VHDL-FPGA-Verilog list

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ADD_SUB Downloaded：0: floating point fused add-subtract unit
Date : 2025-08-21 Size : 2kb User : David
DE2_115_Audio Downloaded：0: DE2-115 development board audio recorders verilog HDL code
Date : 2025-08-21 Size : 1.82mb User : 张海军
DE2_115_NIOS_DEVICE_LED Downloaded：0: DE2-115 development board LED lamp design Verilog HDL language
Date : 2025-08-21 Size : 3.95mb User : 张海军
DE2_115_NIOS_HOST_MOUSE_VGA Downloaded：0: DE2-115 development board VGA verilog HDL design
Date : 2025-08-21 Size : 4.09mb User : 张海军
DE2_115_PS2_DEMO Downloaded：0: The DE2-115 development board of the PS2 Verilog HDL language design
Date : 2025-08-21 Size : 89kb User : 张海军
xapp1015 Downloaded：0: SDI interface VHDL realize XILINX official website design reference
Date : 2025-08-21 Size : 596kb User : 王凯
pailiezuhe Downloaded：0: Fpga-based multi-function digital clock, and with the 1602 show, 24 hours, adjustable hours, minutes, seconds
Date : 2025-08-21 Size : 160kb User : 水茜
ddr2 Downloaded：0: Based on the Xilinx Spartan-3A DSP DDR2 controller
Date : 2025-08-21 Size : 11.57mb User : 朱义
FIFO Downloaded：0: Good FIFO learning materials, starting from the most simple structure, teach you how to design a FIFO.
Date : 2025-08-21 Size : 549kb User : 李路路
1602 Downloaded：0: Verilog-based LCD initialization procedure. This procedure can initialize the based FPGA module 1602.
Date : 2025-08-21 Size : 5kb User : 李路路
FPGA Downloaded：0: The complete collection of questions and of the FPGA beginners, within the there are 27 valuable an instance of, let you relax lightly learn to the FPGA.
Date : 2025-08-21 Size : 1.24mb User : 李路路
GPSDECODE Downloaded：0: Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese
Date : 2025-08-21 Size : 4kb User : 乐百事

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