VHDL-FPGA-Verilog List Page 1156

VHDL-FPGA-Verilog list

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verilog-HDL--LCD-display- Downloaded：0: using verilog HDL to LCD display
Date : 2025-08-21 Size : 2kb User : gx
shuzipinlvji Downloaded：0: Design a frequency meter measuring the frequency of the square wave signal, the measurement frequency range is 0 ~ In 999999Hz The results are shown in decimal.
Date : 2025-08-21 Size : 108kb User : miqiuso
Carry_Select_Adder_Verilog Downloaded：0: Carry Select Adder. Verilog fulfilled. Three testbenches included.
Date : 2025-08-21 Size : 3kb User : 张昊溢
VeriRISC_CPU_Verilog Downloaded：0: This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
Date : 2025-08-21 Size : 9kb User : 张昊溢
bch_dec Downloaded：0: The double error correcting (DEC) BCH encoder/decoder IP cores.
Date : 2025-08-21 Size : 1.05mb User : luobing
rs232 Downloaded：0: Serial transmission, the transmission protocol for RS232. RS-232C standard communication protocol is developed with the EIA (Electronic Industries Association) BELL companies in the United States, published in 1969.
Date : 2025-08-21 Size : 3kb User : 陈恺
32_by_8_RAM Downloaded：0: 32 by 8 RAM. Testbench included.
Date : 2025-08-21 Size : 3kb User : 张昊溢
m_seq Downloaded：0: Verilog HDL m_seq
Date : 2025-08-21 Size : 1.85mb User : Joe
自动电梯控制 Downloaded：0: 基于vhdl的电梯控制。对于控制电梯的上升与下降
Date : 2013-04-19 Size : 5.02mb User : 546154790@qq.com
C6416DSK Downloaded：0: DSP image processing program imlib library use skills
Date : 2025-08-21 Size : 1.2mb User : wangxingbin
channel_loss Downloaded：0: IF digital receiver can help U understand the principle of digital receiver.
Date : 2025-08-21 Size : 2.32mb User : 张昉璞
internet_test Downloaded：0: Xilinx SP605 board, network port design. echo design, implementation, receiving single character and returns the output from the serial port at the same time
Date : 2025-08-21 Size : 11.81mb User : zhangshuo

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