Shift register design the entire circuit is completed by a master timing process each rising edge of the clock, according to the value of the mode [1:0] is cleared, the left or right to operate in the master timing process completed by the case statement shift operation to complete the 8-digit hexadecimal number of bit-wise move for .... loop statement.

6\bidirection_reg.asm.rpt
.\bidirection_reg.done
.\bidirection_reg.fit.rpt
.\bidirection_reg.fit.smsg
.\bidirection_reg.fit.summary
.\bidirection_reg.flow.rpt
.\bidirection_reg.map.rpt
.\bidirection_reg.map.summary
.\bidirection_reg.pin
.\bidirection_reg.pof
.\bidirection_reg.qpf
.\bidirection_reg.qsf
.\bidirection_reg.qws
.\bidirection_reg.sim.rpt
.\bidirection_reg.sof
.\bidirection_reg.tan.rpt
.\bidirection_reg.tan.summary
.\bidirection_reg.vhd
.\bidirection_reg.vhd.bak
.\bidirection_reg.vwf
.\db\bidirection_reg.asm.qmsg
.\..\bidirection_reg.asm.rdb
.\..\bidirection_reg.asm_labs.ddb
.\..\bidirection_reg.cbx.xml
.\..\bidirection_reg.cmp.bpm
.\..\bidirection_reg.cmp.cdb
.\..\bidirection_reg.cmp.ecobp
.\..\bidirection_reg.cmp.hdb
.\..\bidirection_reg.cmp.kpt
.\..\bidirection_reg.cmp.logdb
.\..\bidirection_reg.cmp.rdb
.\..\bidirection_reg.cmp.tdb
.\..\bidirection_reg.cmp0.ddb
.\..\bidirection_reg.cmp2.ddb
.\..\bidirection_reg.cmp_merge.kpt
.\..\bidirection_reg.db_info
.\..\bidirection_reg.eco.cdb
.\..\bidirection_reg.eds_overflow
.\..\bidirection_reg.fit.qmsg
.\..\bidirection_reg.fnsim.cdb
.\..\bidirection_reg.fnsim.hdb
.\..\bidirection_reg.fnsim.qmsg
.\..\bidirection_reg.hier_info
.\..\bidirection_reg.hif
.\..\bidirection_reg.lpc.html
.\..\bidirection_reg.lpc.rdb
.\..\bidirection_reg.lpc.txt
.\..\bidirection_reg.map.bpm
.\..\bidirection_reg.map.cdb
.\..\bidirection_reg.map.ecobp
.\..\bidirection_reg.map.hdb
.\..\bidirection_reg.map.kpt
.\..\bidirection_reg.map.logdb
.\..\bidirection_reg.map.qmsg
.\..\bidirection_reg.map_bb.cdb
.\..\bidirection_reg.map_bb.hdb
.\..\bidirection_reg.map_bb.logdb
.\..\bidirection_reg.pre_map.cdb
.\..\bidirection_reg.pre_map.hdb
.\..\bidirection_reg.rpp.qmsg
.\..\bidirection_reg.rtlv.hdb
.\..\bidirection_reg.rtlv_sg.cdb
.\..\bidirection_reg.rtlv_sg_swap.cdb
.\..\bidirection_reg.sgate.rvd
.\..\bidirection_reg.sgate_sm.rvd
.\..\bidirection_reg.sgdiff.cdb
.\..\bidirection_reg.sgdiff.hdb
.\..\bidirection_reg.sim.cvwf
.\..\bidirection_reg.sim.hdb
.\..\bidirection_reg.sim.qmsg
.\..\bidirection_reg.sim.rdb
.\..\bidirection_reg.simfam
.\..\bidirection_reg.sld_design_entry.sci
.\..\bidirection_reg.sld_design_entry_dsc.sci
.\..\bidirection_reg.smart_action.txt
.\..\bidirection_reg.syn_hier_info
.\..\bidirection_reg.tan.qmsg
.\..\bidirection_reg.tis_db_list.ddb
.\..\logic_util_heursitic.dat
.\..\mux_umc.tdf
.\..\prev_cmp_bidirection_reg.asm.qmsg
.\..\prev_cmp_bidirection_reg.fit.qmsg
.\..\prev_cmp_bidirection_reg.map.qmsg
.\..\prev_cmp_bidirection_reg.qmsg
.\..\prev_cmp_bidirection_reg.sim.qmsg
.\..\prev_cmp_bidirection_reg.tan.qmsg
.\..\wed.wsf
.\incremental_db\compiled_partitions\bidirection_reg.root_partition.cmp.cdb
.\..............\...................\bidirection_reg.root_partition.cmp.dfp
.\..............\...................\bidirection_reg.root_partition.cmp.hdb
.\..............\...................\bidirection_reg.root_partition.cmp.kpt
.\..............\...................\bidirection_reg.root_partition.cmp.logdb
.\..............\...................\bidirection_reg.root_partition.cmp.rcfdb
.\..............\...................\bidirection_reg.root_partition.cmp.re.rcfdb
.\..............\...................\bidirection_reg.root_partition.map.cdb
.\..............\...................\bidirection_reg.root_partition.map.dpi
.\..............\...................\bidirection_reg.root_partition.map.hdb
.\..............\...................\bidirection_reg.root_partition.map.kpt
.\..............\README
.\..............\compiled_partitions

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