VHDL-FPGA-Verilog List Page 1143

VHDL-FPGA-Verilog list

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z80_latest.tar Downloaded：0: Vhdl design z80 for altera users
Date : 2025-08-21 Size : 1.77mb User : alexsandre
Arbi Downloaded：0: this the code for arbiters used for master and slave foermat
Date : 2025-08-21 Size : 6kb User : partydecode
adder-4 Downloaded：0: 4-bit adder 4 binary bits adding quick and easy
Date : 2025-08-21 Size : 236kb User : 蓝狼
fsk1 Downloaded：0: Achieve some of structures FSK modulation system
Date : 2025-08-21 Size : 85kb User : 冯可
frequency-and--fft Downloaded：0: Contains the frequency sampling part of the spectrum analyzer, FFT the reverse order part NIOSII of the program.
Date : 2025-08-21 Size : 2kb User : 冯可
Lab1 Downloaded：0: DE2-70 seven-segment LED
Date : 2025-08-21 Size : 509kb User : 薛炜澎
LCD_1602 Downloaded：0: The verilog lcd1602 module code, as long as it is entered, input data can be displayed.
Date : 2025-08-21 Size : 2kb User : 赖焕宁
LED_display Downloaded：0: verilog optimized LED digital display module, two written comparison.
Date : 2025-08-21 Size : 1kb User : 赖焕宁
clock Downloaded：0: VHDL write clock, display time, basic functions
Date : 2025-08-21 Size : 1kb User : nar
clock Downloaded：0: Alarm Clock using quartus2 software programming, adjust the time, set the alarm, the whole point timekeeping function, the whole project package
Date : 2025-08-21 Size : 1.01mb User : nar
iic_v2_00_a Downloaded：0: Sailin Si FPGA-based IIC interface design to support the host from the machine, multi-master communication bus features, including the datasheet, C language source code.
Date : 2025-08-21 Size : 606kb User : 曾建明
ser_to_4per Downloaded：0: Data string and conversion, by the string of code is converted to 4-bit parallel code, the code in Verilog, and after the Quartus simulation
Date : 2025-08-21 Size : 176kb User : 杨勇

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