VHDL-FPGA-Verilog List Page 1140

VHDL-FPGA-Verilog list

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johnson Downloaded：0: Johnson count is a more advanced Marquee can control the direction of the light
Date : 2025-08-21 Size : 382kb User : 廊桥拾梦
open_free_list_latest.tar Downloaded：0: Its a code for authentication to a memory related topic of the ddr series in the line to achive desired output
Date : 2025-08-21 Size : 8kb User : partydecode
sys_rst Downloaded：0: A PLL and system reset, general can be used
Date : 2025-08-21 Size : 2.42mb User : 廊桥拾梦
dram_latest.tar Downloaded：0: Its a code for authentication to a memory related topic of the ddr series in the line to achive desired output
Date : 2025-08-21 Size : 4kb User : partydecode
vhdl_7-show Downloaded：0: vhdl control board led, beginners can refer to a piece of code to complete the basic functions of the 7-segment display,
Date : 2025-08-21 Size : 115kb User : tzx
verilog-pll Downloaded：0: The multiplier circuit file by verilog introduced DP
Date : 2025-08-21 Size : 1.26mb User : loadziliao
I2C Downloaded：0: I2C controller VHDL implementation
Date : 2025-08-21 Size : 3.14mb User : huangyu
I2C-bus-based-on-FPGA Downloaded：0: I2C bus based on FPGA design using Verilog language, ISE environment containing simulation results
Date : 2025-08-21 Size : 174kb User : huangyu
Async-FIFO-VHDL Downloaded：0: The asynchronous FIFO VHDL code implementation, including: async_fifo_show_ahead.vhd, async_fifo_show_ahead_rd_task_logic.vhd, async_fifo_show_ahead_wr_task_logic.vhd, sync_r2w.vhd, sync_ram_std_dc.vhd, sync_w2r.vhd
Date : 2025-08-21 Size : 7kb User : taxi
FPGA_DDS Downloaded：0: This procedure is based on FPGA DDS arbitrary waveform output, has already been compiled
Date : 2025-08-21 Size : 19kb User : 杨辉
cordic Downloaded：0: codic algorithm unit
Date : 2025-08-21 Size : 2kb User : 李强
LPF_module Downloaded：0: Verilog to achieve the low-pass filter with adjustable bandwidth
Date : 2025-08-21 Size : 1kb User : 李强

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