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[Crack Hack] mini_aes

Description: aes算法的verilog hdl实现，供给大家作为参考 。-Orangk'aes algorithm verilog hdl realized, we supply as a reference.
Platform: | Size: 240640 | Author: 杨忠宇 | Hits:

[VHDL-FPGA-Verilog] pio_top

Description: 这个verilog代码是一个输入输出经典的例子。大家一起参考。-the verilog code input and output is a classic example. Together reference.
Platform: | Size: 528384 | Author: chenliang | Hits:

[VHDL-FPGA-Verilog] ClockOut

Description: 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
Platform: | Size: 1024 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] NumClock

Description: 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理大月小月，可手动任意设置年月日），秒表（包括开始、暂停和清零）。-based Altera FPGA series (Cyclone EP1C3T144C8) , Verilog HDL, MAX7219 Digital Display chips, 4x4 matrix keyboard, TDA2822 chip power amplifier and loudspeakers of the "Electronic Circuit Design
Platform: | Size: 23552 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] usb_2

Description: usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
Platform: | Size: 196608 | Author: lious | Hits:

[VHDL-FPGA-Verilog] fcout

Description: 频率计源代码，性能很好，verilog写的，顶层原理图，底层语言写的，效果很好，开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus
Platform: | Size: 293888 | Author: 苏纳 | Hits:

[Windows CE] DDSFPGA_cylone

Description: dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
Platform: | Size: 637952 | Author: 苏纳 | Hits:

[VHDL-FPGA-Verilog] verilog09090

Description: 5本关于verilog的好书，内容很全面，希望对学习有帮助！-five books on verilog as very comprehensive, and I hope to learn from it!
Platform: | Size: 1206272 | Author: 安安 | Hits:

[VHDL-FPGA-Verilog] verilog232423489

Description: verilog hdl教程135例，例子很好，对新学的很有帮助-verilog hdl Guide 135 cases, very good example of the new study helpful
Platform: | Size: 173056 | Author: 安安 | Hits:

[VHDL-FPGA-Verilog] cmos_FPGA

Description: 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame
Platform: | Size: 1024 | Author: margie | Hits:

[VHDL-FPGA-Verilog] verilog_Divide

Description: 这是我下的一个用verilog实现的除法代码-This is the one I use to achieve the verilog code division
Platform: | Size: 7168 | Author: | Hits:

[VHDL-FPGA-Verilog] cf_fft_2048v

Description: 基于FPGA的2048点FFT的verilog实现的源代码。-FPGA-based 2048-point FFT verilog the source code.
Platform: | Size: 26624 | Author: elber | Hits:

[VHDL-FPGA-Verilog] FIR_filter_DA_machine

Description: 用verilog 代码编写的179阶FIR数字滤波器，采用分布式算法实现-verilog code used to prepare the 179 band FIR digital filters, using Distributed Algorithms
Platform: | Size: 1024 | Author: a | Hits:

[ELanguage] async_transmitter

Description: 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
Platform: | Size: 1024 | Author: weixing | Hits:

[ELanguage] async_receiver

Description: 用verilog实现rs232 receiveri -with verilog achieve rs232 receiveri
Platform: | Size: 1024 | Author: weixing | Hits:

[Embeded-SCM Develop] viterbi_decoder_sources_code_verilog

Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Platform: | Size: 44032 | Author: 林四昆 | Hits:

[File Format] verilog_testbench_preliminary

Description: verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
Platform: | Size: 60416 | Author: 刘彦 | Hits:

[VHDL-FPGA-Verilog] CommandResponse

Description: verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
Platform: | Size: 1024 | Author: hanjian | Hits:

[VHDL-FPGA-Verilog] 8251_8055_verilog

Description: 8251和8055的verilog源码，可进行综合和仿真，是学习SOC的好资料！-8251 and 8055 verilog the source, and integrated simulation, SOC is a good learning information!
Platform: | Size: 13312 | Author: wind | Hits:
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