Location:
Search - verilog
Search list
Description: verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
Platform: |
Size: 236544 |
Author: 章风 |
Hits:
Description: 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.
Platform: |
Size: 5120 |
Author: lee |
Hits:
Description: Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30.
Uses Verilog description with synthesizable RTL modelling.
Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.
-Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: |
Size: 14336 |
Author: 许茹芸 |
Hits:
Description: jpeg解码电路，是verilog编写的，可以综合，很有实用价值。-jpeg decoder circuit, is prepared verilog, synthesis, very practical value.
Platform: |
Size: 181248 |
Author: blueli |
Hits:
Description: arm9 架构简单core实现，可以综合，有实现步骤和说明，verilog代码编写。-arm9 core framework to achieve a simple, comprehensive, implementation steps and notes verilog code prepared.
Platform: |
Size: 951296 |
Author: blueli |
Hits:
Description: intel 8088 架构的verilog代码，可以综合下载，在fpga上实现8088调试。-intel 8088 verilog structure of the code can be integrated download, fpga achieved in 8088 debugging.
Platform: |
Size: 240640 |
Author: blueli |
Hits:
Description: arm7timi架构的verilog代码，可以仿真，通过学习，可以掌握arm7内部架构。-arm7timi verilog structure of the code can be simulated, through learning, be able arm7 internal structure.
Platform: |
Size: 677888 |
Author: blueli |
Hits:
Description: ddr2 controller, verilog source code from xilinx
Platform: |
Size: 347136 |
Author: Hubert |
Hits:
Description: Verilog HDL硬件描述语言
01简介.PDF
02HDL指南.PDF
03语言要素.PDF
04表达式.PDF
05门电平模型化.PDF
06用户定义原语.PDF
07数据流模型化.PDF
08行为建模.PDF
09结构建模.PDF
10其它论题.PDF
11验证.PDF
12建模实例.PDF
13语法参考.PDF-Verilog HDL Hardware Description Language Introduction 01. PDF 02HDL Guide. PDF 0 3 language elements. PDF 04 expressions. PDF 05-level modeling. PDF 06 user-defined primitives. P DF 07 data flow modeling. PDF 08 behavior modeling. PDF 09 modeling structure. PDF 10 other topics . PDF 11 certification. PDF 12 model. PDF 13 syntax reference. PDF
Platform: |
Size: 4837376 |
Author: 高 |
Hits:
Description: 这是用Verilog语言编写AV型LCD屏的驱动程序CPLD上运行并调试成功的。可用作数字到模拟LCD转换-Verilog language AV-screen LCD driver CPLD debugging and running successful. Can be used to simulate LCD digital conversion
Platform: |
Size: 1024 |
Author: |
Hits:
Description: 4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.-4-7segment led display Verilog code. Impl emented at Stratix EP1S25 DSP development boar d.
Platform: |
Size: 2048 |
Author: iamz |
Hits:
Description: 一个关于MEMORY设计的原代码,使用VERILOG编写的 希望对大家有些帮助-one of the original Memory design code prepared by the use of verilog we hope to help some
Platform: |
Size: 26624 |
Author: 王平 |
Hits:
Description: 用verilog编写适中分频器
并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
Platform: |
Size: 25600 |
Author: |
Hits:
Description: hmac的verilog代码, 通过控制字选择进行sha1运算或hmac运算-hmac the verilog code word through the control options or hmac sha1 Operational Operational
Platform: |
Size: 559104 |
Author: lijialu |
Hits:
Description: 王金明的Verilog HDL程序集合，包含各个常用的程序-guo Verilog HDL procedures set includes all commonly used procedures
Platform: |
Size: 113664 |
Author: weishenghe |
Hits:
Description: 一篇有用的Verilog语言综合问题研究-a useful comprehensive Verilog language study
Platform: |
Size: 272384 |
Author: wrrkaixin |
Hits:
Description: 基于Verilog-HDL的硬件电路的实现
9.1 简单的可编程单脉冲发生器
9.1.1 由系统功能描述时序关系
9.1.2 流程图的设计
9.1.3 系统功能描述
9.1.4 逻辑框图
9.1.5 延时模块的详细描述及仿真
9.1.6 功能模块Verilog-HDL描述的模块化方法
9.1.7 输入检测模块的详细描述及仿真
9.1.8 计数模块的详细描述
9.1.9 可编程单脉冲发生器的系统仿真
9.1.10 可编程单脉冲发生器的硬件实现
9.1.11 关于电路设计中常用的几个有关名词
-based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Description logic diagram 9.1.5 9.1.4 Delay Module detailed description and simulation of 9.1. 6 functional modules Verilog-HDL description of the modular input method detection module 9.1.7 detailed 9.1.8 Description and Simulation module counting a detailed description 9.1.9 programmable pulse generator system 9.1.10 Simulation programmable pulse generator hardware on the circuit design 9.1.11 Constant Some of the terminology
Platform: |
Size: 4096 |
Author: 宁宁 |
Hits:
Description: 基于Verilog-HDL的硬件电路的实现
9.2 具有LCD显示单元的可编程单脉冲发生器
9.2.1 LCD显示单元的工作原理
9.2.2 显示逻辑设计的思路与流程
9.2.3 LCD显示单元的硬件实现
9.2.4 可编程单脉冲数据的BCD码化
9.2.5 task的使用方法
9.2.6 for循环语句的使用方法
9.2.7 二进制数转换BCD码的硬件实现
9.2.8 可编程单脉冲发生器与显示单元的接口
9.2.9 具有LCD显示单元的可编程单脉冲发生器的硬件实现
9.2.10 编译指令-"文件包含"处理的使用方法
-based on Verilog-HDL hardware Circuit of 9.2 LCD display module with the series Single-Pulse Generator 9.2.1 LCD display module Principle 9.2.2 shows the logic design Thinking and Process 9.2.3 LCD display module hardware 9.2.4 programmable single pulse data BCD of the task 9.2.5 9.2.6 for the use of the phrase cycle use 9.2.7 binary conversion of BCD programmable hardware 9.2.8 single pulse generator with a said unit 9.2.9 interface with the LCD display module programmable pulse generator hardware 9 .2.10 compiler directives- "document includes" the use of
Platform: |
Size: 5120 |
Author: 宁宁 |
Hits:
Description: 基于Verilog-HDL的硬件电路的实现
9.3 脉冲计数与显示
9.3.1 脉冲计数器的工作原理
9.3.2 计数模块的设计与实现
9.3.3 parameter的使用方法
9.3.4 repeat循环语句的使用方法
9.3.5 系统函数$random的使用方法
9.3.6 脉冲计数器的Verilog-HDL描述
9.3.7 特定脉冲序列的发生
9.3.8 脉冲计数器的硬件实现
-based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5- EC $ random function of the use of pulse counter 9.3.6 Verilog-HDL depiction 9.3.7 to specific pulse sequences occurred pulse counter 9.3.8 Hardware Implementation
Platform: |
Size: 4096 |
Author: 宁宁 |
Hits:
Description: 基于Verilog-HDL的硬件电路的实现
9.4 脉冲频率的测量与显示
9.4.1 脉冲频率的测量原理
9.4.2 频率计的工作原理
9.4.3 频率测量模块的设计与实现
9.4.4 while循环语句的使用方法
9.4.5 门控信号发生模块的设计与实现
9.4.6 频率计的Verilog-HDL描述
9.4.7 频率计的硬件实现
-based on Verilog-HDL hardware Circuit of 9.4 pulse frequency measurement and display 9.4.1 pulse frequency measurement frequency 9.4.2 principle, the principle 9.4.3 Frequency Measurement Module Design and Implementation 9.4.4 cycle statement while the use 9.4.5 gating signal occurred Module Design and Implementation 9.4.6 frequency of Verilog-HDL description 9.4. 7 frequency of hardware
Platform: |
Size: 2048 |
Author: 宁宁 |
Hits: