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Description: 基于Verilog-HDL的硬件电路的实现
9.5 脉冲周期的测量与显示
9.5.1 脉冲周期的测量原理
9.5.2 周期计的工作原理
9.5.3 周期测量模块的设计与实现
9.5.4 forever循环语句的使用方法
9.5.5 disable禁止语句的使用方法
9.5.6 时标信号发生模块的设计与实现
9.5.7 周期计的Verilog-HDL描述
9.5.8 周期计的硬件实现
9.5.9 周期测量模块的设计与实现之二
9.5.10 改进型周期计的Verilog-HDL描述
9.5.11 改进型周期计的硬件实现
9.5.12 两种周期计的对比
-based on Verilog-HDL hardware Circuit of 9.5 pulse cycle of measurement and display 9.5.1 pulse cycle 9.5.2 cycle measurement principle, the principle 9.5.3 cycle measurement Module Design and Implementation 9.5.4 statement cycle forever the use 9.5.5 di sable statement ban on the use 9.5.6 at the beacon signal occurred Module Design and Implementation 9.5 .7 cycle of Verilog-HDL description 9.5.8 cycle of hardware 9.5. 9 cycle measurement module design and realization of two 9.5.10 Improved cycle of Verilog- HDL description 9.5.11 Improved cycle of hardware 9.5.12 two cycles of contrast
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Size: 5120 |
Author: 宁宁 |
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Description: 基于Verilog-HDL的硬件电路的实现
9.6 脉冲高电平和低电平持续时间的测量与显示
9.6.1 脉冲高电平和低电平持续时间测量的工作原理
9.6.2 高低电平持续时间测量模块的设计与实现
9.6.3 改进型高低电平持续时间测量模块的设计与实现
9.6.4 begin声明语句的使用方法
9.6.5 initial语句和always语句的使用方法
9.6.6 时标信号发生模块的设计与实现
9.6.7 脉冲高低电平持续时间测量的Verilog-HDL描述
9.6.8 脉冲高低电平持续时间测量的硬件实现
-Verilog-HDL-based hardware circuits to achieve 9.6 high and low pulse duration measurement and 9.6.1 show the high and low pulse duration of the working principle of measuring the high-low 9.6.2 duration measurement module 9.6.3 Design and Implementation of Improved Measurement of the high-low duration of the Design and Implementation of Module 9.6.4 begin the use of declaration statements 9.6.5 initial statement and statements always use 9.6.6 beacon signal occurs when the module design and 9.6.7 to achieve the high-low pulse duration measurement of Verilog-HDL description 9.6.8 high-low pulse duration measurement hardware implementation
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Size: 5120 |
Author: 宁宁 |
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Description: 基于Verilog-HDL的硬件电路的实现
9.7 步进电机的控制
9.7.1 步进电机驱动的逻辑符号
9.7.2 步进电机驱动的时序图
9.7.3 步进电机驱动的逻辑框图
9.7.4 计数模块的设计与实现
9.7.5 译码模块的设计与实现
9.7.6 步进电机驱动的Verilog-HDL描述
9.7.7 编译指令-"宏替换`define"的使用方法
9.7.8 编译指令-"时间尺度`timescale"的使用方法
9.7.9 系统任务-"$finish"的使用方法
9.7.10 步进电机驱动的硬件实现
-based on Verilog-HDL hardware Circuit of 9.7 Stepper Motor Control 9.7 .1 stepper motor-driven logic symbols 9.7.2 stepper motor driven map the chronology-- Step 9.7.3 Machine-driven logic diagram 9.7.4 Counting Module Design and Implementation 9.7.5 decoding module design and Implementation 9.7.6 stepper motor driven Verilog-HDL Compiler means locale 9.7.7 Description Order- "macro substitution` define "the use 9.7.8 compiler directives-" The time scale `tim escale "use 9.7.9 system tasks-" $ finish "to use 9.7.10 stepper motor drive hardware
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Size: 2048 |
Author: 宁宁 |
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Description: 基于Verilog-HDL的硬件电路的实现
9.8 基于256点阵的汉字显示
9.8.1 单个静止汉字显示的设计原理及其仿真实现
9.8.2 单个静止汉字显示的硬件实现
9.8.3 多个静止汉字显示的设计原理及其硬件实现
9.8.4 单个运动汉字显示的设计原理及其硬件实现
9.8.5 多个运动汉字显示的设计原理及其硬件实现
-based on Verilog-HDL hardware Circuit of 9.8 based on the lattice of 256 Chinese character display 9.8.1 static single Chinese character display and the design principle Simulation 9.8.2 single Chinese character was geostationary said the number of hardware 9.8.3 static display Chinese characters and hardware design principle to achieve single-9.8.4- Movement of the Chinese character display and hardware design principle to achieve a number of campaigns 9.8.5 Chinese character display and the design principle Hardware Implementation
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Size: 1024 |
Author: 宁宁 |
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Description: 基本运算逻辑和它们的Verilog HDL模型-basic arithmetic logic and their Verilog HDL model
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Size: 70656 |
Author: 苏航 |
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Description: 我收藏的一些小技巧，适合刚开始学习verilog的朋友，养成好的编写习惯很重要哦~-collection of some small skills, suitable for the beginning of the study verilog friends, develop good habits is very important to prepare oh ~
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Size: 7168 |
Author: 薇 |
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Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
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Size: 8427520 |
Author: heartbeat |
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Description: Verilog.pdf。有Verilog的大量范例。适合于想动手设计芯片的人。-Verilog.pdf. Verilog is a large number of examples. Suited to fight in the chip design.
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Size: 113664 |
Author: 苗权 |
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Description: 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
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Size: 4096 |
Author: MingCheng |
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Description: 8BIT MCU 的VERILOG代码实现，具有一定的参考价值-8BIT MCU verilog code realized, with some reference value
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Size: 79872 |
Author: 李书鹏 |
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Description: 《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design
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Size: 1765376 |
Author: 孟繁雪 |
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Description: 十六位超前进位加法器，Verilog HDL-16-ahead adder, Verilog HDL
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Size: 214016 |
Author: Li Yanwei |
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Description: 用verilog硬件描述语言编写的16位数模转换器的源代码，可以综合-with verilog hardware description language of 16 Digital to Analog source code can be integrated
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Size: 1024 |
Author: awp |
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Description: 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
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Size: 51200 |
Author: 刘海 |
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Description: verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
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Size: 656384 |
Author: lumingzhi |
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Description: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
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Size: 9216 |
Author: mingming |
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Description: Verilog and VHDL状态机设计，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding
presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
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Size: 113664 |
Author: mingming |
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Description: Verilog 程序例子 王金明：《Verilog HDL程序设计教程》程序例子，带说明。
-Verilog procedures guo examples : "Verilog HDL Design Guide" procedures example, take note.
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Size: 160768 |
Author: mingming |
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Description: 用verilog设计密勒解码器
一、题目：
设计一个密勒解码器电路
二、输入信号：
1． DIN：输入数据
2． CLK：频率为2MHz的方波，占空比为50％
3． RESET：复位信号，低有效
三、输入信号说明：
输入数据为串行改进密勒码，每个码元持续时间为8μs，即16个CLK时钟；数据流是由A、B、C三种信号组成；
A：前8个时钟保持“1”，接着5个时钟变为“0”，最后3个时钟为“1”。
B：在整个码元持续时间内都没有出现“0”，即连续16个时钟保持“1”。
C：前5个时钟保持“0”，后面11个时钟保持“1”。
改进密勒码编码规则如下：
如果码元为逻辑“1”，用A信号表示。
如果码元为逻辑“0”，用B信号表示，但以下两种特例除外：如果出现两个以上连“0”，则从第二个“0”起用C信号表示；如果在“通信起始位”之后第一位就是“0”，则用C信号表示，以下类推；
“通信起始位”，用C信号表示；
“通信结束位”，用“0”及紧随其后的B信号表示。
“无数据”，用连续的B信号表示。-err
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Size: 211968 |
Author: mingming |
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Description: Verilog教程中文版-Guide to the Chinese version of Verilog
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Size: 798720 |
Author: 王国华 |
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