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Search - rs encoder Verilog

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[ELanguage] rs-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien - search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data - rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 44917 | Author: zs8292 | Hits:

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5100 | Author: 王锋 | Hits:

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[ELanguage] rs-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 45056 | Author: zs8292 | Hits:

[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 76800 | Author: 王文 | Hits:

[VHDL-FPGA-Verilog] encode

Description: Quartus下的RS（5，3）编码器的源程序，用Verilog语言编写。-Quartus under the RS (5,3) encoder source code, using Verilog language.
Platform: | Size: 3072 | Author: 桃子 | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[VHDL-FPGA-Verilog] rs_enc

Description: Verilog code for RS-(255,239) encoder.
Platform: | Size: 3072 | Author: sharat | Hits:

[matlab] learn_RS_coding

Description: 自己根据网上已有程序改写的(127,115)RS编码，有详细的注释及对FPGA实现算法的改写(参考try123.m)，希望可以让大家少走弯路-(127,115) rs encoder/decorder with detailed annotations.
Platform: | Size: 51200 | Author: yan | Hits:

[VHDL-FPGA-Verilog] fec_enc

Description: 实现RS（255，239）的编码器，语言为Verilog。-Implementation RS (255,239) encoder, language is Verilog.
Platform: | Size: 1024 | Author: 无名 | Hits:

[VHDL-FPGA-Verilog] RS_coder

Description: 基于verilog的RS编码器 绝对实用-Based on the RS encoder verilog absolute utility
Platform: | Size: 178176 | Author: 吴 | Hits:

[VHDL-FPGA-Verilog] ff_mul

Description: 基于rs编码器的verilog伽罗华域乘法器设计-Rs encoder based on Galois field multiplier verilog
Platform: | Size: 1024 | Author: 吴 | Hits:

[VHDL-FPGA-Verilog] RScoder

Description: 基于FPGA的RS编码器设计，verilog hdl语言。-RS encoder FPGA-based design, verilog hdl language.
Platform: | Size: 12288 | Author: 小明 | Hits:

[Other] rs_encoder_decoder

Description: RS编解码源程序，有详细的VERILOG程序，用于纠错-RS encoder and decoder
Platform: | Size: 32768 | Author: williamyang | Hits:

[VHDL-FPGA-Verilog] RS_bmq

Description: 在QuartusII软件中用Verilog HDL编写的RS编码器的源代码-The RS encoder Verilog HDL prepared with in QuartusII software source code
Platform: | Size: 15360 | Author: 徐鑫 | Hits:

[VHDL-FPGA-Verilog] RS

Description: 通过verilog hdl语言实现RS编码器与译码器的设计-Verilog hdl language through the RS encoder and decoder design
Platform: | Size: 26624 | Author: 李永超 | Hits:

[VHDL-FPGA-Verilog] RS_enc

Description: RS编码器设计，使用Verilog实现。-RS encoder design, Verilog implementation.
Platform: | Size: 15360 | Author: 王坤 | Hits:

[VHDL-FPGA-Verilog] rsencoder.tar

Description: RS Encoder RTL verilog Code
Platform: | Size: 4096 | Author: richman | Hits:

[VHDL-FPGA-Verilog] RS

Description: 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)
Platform: | Size: 3862528 | Author: heyu7892020 | Hits:

[Communication-Mobile] rs_15_11

Description: ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)
Platform: | Size: 14336 | Author: Ericxgj | Hits:
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