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[Embeded-SCM Develop] Xinlinx_ISE_study

Description: 用中文介绍Xilinx公司FPGA/CPLD的集成开发环境－ISE软件的简单使用 -Introduction to Chinese Xilinx Inc. FPGA/CPLD integrated development environment-ISE software simple to use
Platform: | Size: 825344 | Author: Kuben | Hits:

[VHDL-FPGA-Verilog] ddr

Description: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Platform: | Size: 1022976 | Author: yuling | Hits:

[Other] ise_lecture

Description: ise的简单使用说明，虽然比较简单，至少能够使你开始编写简单的vhdl程序。
Platform: | Size: 277504 | Author: kingbow | Hits:

[Other] ise9tut

Description: VHDL Xilinx ISE 9.1i
Platform: | Size: 1648640 | Author: 孙延腾 | Hits:

[Documents] ise

Description: xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能-Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance
Platform: | Size: 271360 | Author: 江巧微 | Hits:

[Software Engineering] VHDL

Description: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target device Xilinx
Platform: | Size: 297984 | Author: 西西 | Hits:

[Books] XilinxISE6[1]_1ichinese

Description: ise6.1的中文说明，能够在较短的时间内熟悉ise-ise6.1 the Chinese that in a short period of time are familiar with ise
Platform: | Size: 825344 | Author: yugaoshang | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPLD

Description: 在文件夹YL2440_CPLD中有做好的CPLD工程,请用Xilinx ISE 6.2打开.-In the folder have to do a good job YL2440_CPLD the CPLD project, please open the Xilinx ISE 6.2.
Platform: | Size: 686080 | Author: gaofeng | Hits:

[Software Engineering] Timing

Description: 开发环境是QUARTUSI,ISE等FPGA开发工具，本问主要描述FGPA开发过程中需要注意的时序-Development environment is QUARTUSI, ISE and other FPGA development tools, the principal asked to describe the process of developing FGPA need to pay attention to timing
Platform: | Size: 1510400 | Author: horse | Hits:

[VHDL-FPGA-Verilog] dynamic_display

Description: 4 digital LED dynamic display的Verilog HDL源代码，它能动态的显示4位数，为FPGA 的DEBUG 提供便利，非常经典，简单易懂，并且经过了Modelsim/ISE/FPGA(XC3S250ETQ144)验证和实现，好的行为模型就应该大家分享。-4 digital LED dynamic display of the Verilog HDL source code, it can dynamically display 4-digit for the FPGA to facilitate the DEBUG, very classic, easy-to-read, and after Modelsim/ISE/FPGA (XC3S250ETQ144) authentication and realize, good The behavior model should be shared.
Platform: | Size: 257024 | Author: name | Hits:

[VHDL-FPGA-Verilog] 8086FPGA

Description: xilinx ise 7.1下 实现sparten3 basys板上基于8086FPGA软核的吃豆子游戏-xilinx ise 7.1 under sparten3 basys board based on soft-core 8086FPGA eating beans games
Platform: | Size: 2360320 | Author: 朱万里 | Hits:

[VHDL-FPGA-Verilog] ise_book

Description: xilinx ISE 实例代码。可用ISE直接打开-xilinx ISE code examples. ISE can be used directly to open
Platform: | Size: 8278016 | Author: 罗 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库 第二章 调用Xilinx CORE-Generator 第三章 使用Synplify.Pro综合HDL和内核 第四章 综合后的项目执行 第五章 不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Platform: | Size: 218112 | Author: 青岚之风 | Hits:

[VHDL-FPGA-Verilog] usb

Description: 这是个USB 的VHDL 程序，进去直接双击ISE 就可以用了-This is a USB-VHDL procedures, into direct ISE can use double-click the
Platform: | Size: 1644544 | Author: 张亚伟 | Hits:

[Other] aybook.cn_xilizwjc1129

Description: 是一款ISE比较经典的教程，对于出用ise的朋友比较有用-ISE is a relatively classic Guide, for a friend with more useful ise
Platform: | Size: 278528 | Author: 孙军 | Hits:

[VHDL-FPGA-Verilog] convert

Description: 用与生成ISE的IP核的COE文件，一些具体的参数要自己设置一下！
Platform: | Size: 1024 | Author: 1111 | Hits:

[VHDL-FPGA-Verilog] my_dcm

Description: 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连-In the Xilinx ISE environment, configure a DCM components, can view the program is running time. Through the serial port and terminal equipment connected to
Platform: | Size: 710656 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] LVDS

Description: 以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法，底层布局器设计流程，底层布局器中的位置约束，时序分析器的使用方法，时序改进向导的使用等.-LVDS design for example to study the timing analysis ISE as well as the use of low-level device layout method in the bottom of the layout of LVDS device pin to bound methods, the bottom of the layout design flow, the underlying device layout position constraints, timing analyzer use timing to improve the use of the wizard.
Platform: | Size: 129024 | Author: 程凯 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[VHDL-FPGA-Verilog] task_function

Description: 自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过-I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through
Platform: | Size: 235520 | Author: lg | Hits:
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