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Description: 外部FLASH，用于存放图片数据，可以实现qspi访问机制，(Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
AutoBoot power up or reset and execute a Normal or Quad read)
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Size: 1746944 |
Author: Hey123
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Description: test ddr to ddr performance
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Size: 1024 |
Author: litterfish
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Description: 可以测试DM6446的DDR LED NANDFLASH SRAM 等部分(You can test the parts of the DM6446's DDR LED NANDFLASH SRAM and other parts)
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Size: 1939456 |
Author: gob
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Description: This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.
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Size: 2027520 |
Author: serg_86
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Description: This module converts 8 bit SDR flow to 4 bit DDR RGMII flow, proved on Altera Cyclone 3 devices.
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Size: 2045952 |
Author: serg_86
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Description: 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)
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Size: 32524288 |
Author: 刘小娃 |
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Description: JEDC DDR-5 Standard. DDR-5 标准。(JEDC DDR-5 Standard. JESD79-5 DDR5 Spec Early Draft Rev0.1)
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Size: 4538368 |
Author: Vkings |
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Description: DDR RAM DESCRIPTION CODE AND DOCUMENT
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Size: 36864 |
Author: avany |
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Description: axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
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Size: 8192 |
Author: 橙子很好吃 |
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Description: modding ddr 2 sd ram to 800mhz
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Size: 798720 |
Author: redbulx3 |
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Description: 黑金spartan的开发板教程，包含了各类接口如spi，uart，vga的用例，以及各项存储器如flash，ddr的操作方法(spartan 6 example design)
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Size: 19894272 |
Author: 爱的分啥 |
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Description: This project has dependencies in the 'digilent' VHDL library. For your convenience
a local copy of these dependencies are included in the remote_sources directory.
The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup.
The project configures the two cameras on the VmodCAM for maximum resolution
and frame rate, RGB output and video snapshot mode. The DDR memory on-board
the Atlys is used as a frame buffer. The two video feeds from both cameras are
bufferd in the DDR, while the FPGA drives the HDMI out port with either of the
cameras. Switch 7 selects the camera which gets displayed. The resolution of
the cameras (1600x1200) gets cropped to fit the display resolution of 1600x900.
Project built in ISE 13.2, tested in ISE 13.1.
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Size: 13762560 |
Author: domnish |
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Description: Nexys 4 DDR上的鼠标接受测试程序(The mouse acceptance test program on Nexys 4 DDR)
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Size: 5120 |
Author: cocoon |
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Description: 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
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Size: 4935680 |
Author: maxw123456789 |
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Description: JEDEC DDR4 spec 标准，是学习DDR的好资料(JEDEC DDR4 spec, good spec for understanding and studying DDR4)
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Size: 3442688 |
Author: 哎呀123456 |
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Description: 6678工程应用，包含SRIO、net、PCIE、DDR3等接口，可以作为开发的参考文件(6678 engineering applications, including SRIO, net, PCIE, DDR3 and other interfaces, can be used as reference files for development.)
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Size: 3852288 |
Author: 天真天趣 |
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Description: bemanitools 4.25 for iidx/sdvx/ddr/pnm/etc
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Size: 1554432 |
Author: fgsfds123 |
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Description: vivado下的MIG教程,适用于XILINX 7系列FPGA(MIG tutorial under vivado.)
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Size: 4861952 |
Author: 城北的D1B |
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Description: DDR4 SDRAM Specifications from JEDEC STANDARD. ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2).
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Size: 1824071 |
Author: bdebug@gmail.com |
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Description: 海思硬件电路设计资料，主要是3519A DDR设计
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Size: 583168 |
Author: final_aim@163.com |
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