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Description: 莱迪思的DDR控制器源码（包括仿真与说明文档），DDR为MT46V16M8，Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
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Size: 615424 |
Author: 刘佳庆 |
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Description: DM6467及DM6467T芯片在CCS开发环境下测试DDR通讯是否正常的源代码。-DM6467 and DM6467T test DDR code under CCS.
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Size: 58368 |
Author: 王秀 |
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Description: 一个关于音频播放的fpga驱动代码。流程是从sd卡中读取音频文件，然后缓存到DDR中，再通过一定的时序关系让音频WM8731芯片播放-An audio playback on fpga driver code. The process is to read audio files from sd card and then cached to DDR, and then through a certain timing relationships allow playback of audio WM8731 chip
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Size: 215040 |
Author: lilianghua |
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Description: 本代码是基于arm11(s3c6410)开发板，实现nandflash启动，程序运行在DDR中，实现异常向量入口功能，具有按键中断和串口输出功能-The code is based on arm11 (s3c6410) development board to achieve nandflash start, with the keys and serial interrupt output function
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Size: 13312 |
Author: dongpan |
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Description: 达芬奇系列开发板，rs485测试程序，用于检测DSP的rs485接口工作正常-Da Vinci series development board, DDR test program, used to detect between Dsp and rs485 interface to work normally
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Size: 66560 |
Author: 卡卡罗特 |
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Description: Design and implementation of High Speed Pipelined DDR SDRAM memory Controller
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Size: 772096 |
Author: JAGRUTHI M S |
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Description: DDR Ctrlr Interrupt Registers.
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Size: 2048 |
Author: gamuwe |
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Description: 该程序为Altera 公司 DDR DDR2 SDRAM 的IP源程序安装包，非常有价值的东西，借此网址共享下。-The program for Altera Corporation DDR DDR2 SDRAM of IP source installation package, a very valuable thing, whereby the URL Sharing.
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Size: 8764416 |
Author: 刘明 |
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Description: H9DP32A4JJMCGR datasheet
4GB e-NAND Flash + 4Gb Mobile DDR
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Size: 1572864 |
Author: stfuaw |
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Description: Definitions for DDR memories based on JEDEC specs.
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Size: 1024 |
Author: jiumxvon |
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Description: DDR驱动，一个摄像头产品上的ddr驱动程序-ddr driver
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Size: 1024 |
Author: kwok |
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Description: 风河提供的飞思卡尔P2041 VXworks BSP包，完美支持SATA NAND DDR USB MMC PCI等接口-Freescale P2041 VXworks BSP package Wind River provides the perfect support SATA NAND DDR USB MMC PCI interfaces
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Size: 2885632 |
Author: wang |
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Description: 本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High
Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。
本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目
的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。-This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.
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Size: 801792 |
Author: 123 |
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Description: ALLegro绘制PCB时需要进行规则设置，本文基于DDR给大家简要的说明了相关设置要点-ALLegro to rule set, when scale PCB based on DDR briefly illustrates the relevant set points for you
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Size: 219136 |
Author: 564654654 |
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Description: AM335X PRU例子，介绍如何进行PRU与DDR之间的通信-AM335X PRU example, introduce how to communicate beteween PRU and DDR
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Size: 2048 |
Author: 吴侠 |
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Description: Atmel (Multi-port DDR-)SDRAM Controller driver.
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Size: 1024 |
Author: gtnieber |
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Description: DDR Ctrlr Error Registers for Linux v2.13.6.
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Size: 3072 |
Author: cpzsrm |
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Description: DDR addressing details and AC timing parameters JEDEC specs.
-DDR addressing details and AC timing parameters JEDEC specs.
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Size: 1024 |
Author: kycongong |
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Description: switch stack to L1 scratch, prepare for ddr srfr.
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Size: 1024 |
Author: vygendin |
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Description: <用FPGA实现VGA显示>
摘要：本文介绍了一种用FPGA结合DDR SDRAM和单片机，在VGA显示器上显示字符、图形信息的方法。-The realization of VGA display with FPGA
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Size: 239616 |
Author: zblinux |
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