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Description: ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
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Size: 4943872 |
Author: 松鼠 |
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Description: 官网下载的，经过板级验证的ddr control mt45v16m16p源代码，verilog语言设计，希望可以用到系统化设计。-Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design.
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Size: 23552 |
Author: lvhenan |
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Description: DDR控制mt46v16m16芯片的指导性文件-ddr IP core control chip mt46v16m16 guidance document
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Size: 2419712 |
Author: lvhenan |
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Description: 嵌入式设备性能测试工具，可以测试cpu、ddr等性能。-bench mark tool for embeded machine
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Size: 502784 |
Author: wang |
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Description: Micron docfor ddr ram for using DDr ram design
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Size: 115712 |
Author: manimaran |
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Description: pmon的打印信息，有代码的初始化过程，包括TLB，DDR，等等。-pmon print infomation
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Size: 9216 |
Author: 张乐嘉 |
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Description: 龙芯1B开发板的移植代码，包括CPU/DDR/MAC/SPI等设备的驱动程序-Long core 1B development board transplant code, including CPU/DDR/MAC/SPI devices such as the driver
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Size: 99988480 |
Author: vic3223 |
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Description: 完整的DDR控制器设计，包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
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Size: 337920 |
Author: zhangbin |
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Description: 基于TI TMS320DM8168芯片DDR测试程序-Based on TI TMS320DM8168 chip DDR test program
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Size: 77824 |
Author: faye |
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Description: 6410开发板对应的ddr驱动源码，基于裸板开发，对于学习驱动开发是很好的参考示例-6410 development board corresponding to the ddr-driven source, based on the bare board development, learning-driven development is a good reference example
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Size: 4096 |
Author: robertbrown |
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Description: fpga控制CMOS相机ov5640采集图像，包括相机配置，ddr缓存，vga显示三个模块。直接可用-fpga control CMOS camera ov5640 capture images, including camera configuration, ddr cache, vga three display modules. Directly available
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Size: 14336 |
Author: 高文 |
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Description: The Nexys4 DDR board is a complete, ready-to-use digital circuit
development platform based on the latest Artix-7™ Field
Programmable Gate Array (FPGA) Xilinx® . With its large,
high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C),
generous external memories, and collection of USB, Ethernet, and
other ports, the Nexys4 DDR can host designs ranging from
introductory combinational circuits to powerful embedded
processors. Several built-in peripherals, including an
accelerometer, temperature sensor, MEMs digital microphone, a
speaker amplifier, and several I/O devices allow the Nexys4 DDR
to be used for a wide range of designs without needing any other
component-The Nexys4 DDR board is a complete, ready-to-use digital circuit
development platform based on the latest Artix-7™ Field
Programmable Gate Array (FPGA) Xilinx® . With its large,
high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C),
generous external memories, and collection of USB, Ethernet, and
other ports, the Nexys4 DDR can host designs ranging from
introductory combinational circuits to powerful embedded
processors. Several built-in peripherals, including an
accelerometer, temperature sensor, MEMs digital microphone, a
speaker amplifier, and several I/O devices allow the Nexys4 DDR
to be used for a wide range of designs without needing any other
component
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Size: 1024 |
Author: yaseenn |
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Description: 飞思卡尔平台imx6 DDR配置参数配置工具。-Freescale platform imx6 DDR configuration parameter configuration tool.
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Size: 89088 |
Author: 谢志鹏 |
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Description: describe synopsis ommonly use double data rate (DDR) memory IP to boost memory bandwidth, but they
often struggle to meet timing budgets for these high-speed interfaces. Designers who incorporate DDR
IP into systems-on-chip (SoCs) and use external DRAM have little control over the timing c
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Size: 580608 |
Author: hasan |
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Description: 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of
HSTL1 and LVTTL I/O standards
/qdr2/source/qdr2.v > Main module of the QDR memory controller
/qdr2/source/pipeline.v > Pipeline module for increasing performance
/qdr2/source/oddr_xp.v > Output DDR module
/qdr2/source/pll_qdr_sim.v > Pll module for simulation
/qdr2/source/pll_qdr_syn.v > Pll module for synthesis
/qdr2/source/magma.v- 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of
HSTL1 and LVTTL I/O standards
/qdr2/source/qdr2.v > Main module of the QDR memory controller
/qdr2/source/pipeline.v > Pipeline module for increasing performance
/qdr2/source/oddr_xp.v > Output DDR module
/qdr2/source/pll_qdr_sim.v > Pll module for simulation
/qdr2/source/pll_qdr_syn.v > Pll module for synthesis
/qdr2/source/magma.v
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Size: 16384 |
Author: liuxuemin |
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Description: 芯视清C4-30开发板的自检启动代码，里面有Audio_wm,DDR,LCD,PS2,VGA，等多个端口的自检程序-Core visual C4-30 development board self start code, which has Audio_wm, DDR, LCD, PS2, VGA, and many other self inspection procedures
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Size: 582656 |
Author: 程竹 |
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Description: CCS软件平台中的DDR EIMA 外设操作(DDR EIMA peripheral operation in CCS software platform)
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Size: 569344 |
Author: 半笺1900
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Description: DRR3 peripheral test for Microblaze processor on Spartan-6
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Size: 13840384 |
Author: kilometrix
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Description: 全志v3s的datasheet。详细的寄存器说明。
全志v3s介绍：内置64M ddr内存，qfp封装(V3s of datasheet. Detailed register instructions.
Whole chronicles v3s introduction: built in 64M DDR memory, QFP package)
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Size: 5023744 |
Author: ______
|
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Description: 测试DDR 稳定性 测试时间为10小时(test the DDR test hour 10)
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Size: 1232896 |
Author: 浅夏
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